|
| 1 | +block/GPRCM: |
| 2 | + items: |
| 3 | + - name: PWREN |
| 4 | + description: Power enable. |
| 5 | + byte_offset: 0 |
| 6 | + fieldset: PWREN |
| 7 | + - name: RSTCTL |
| 8 | + description: Reset Control. |
| 9 | + byte_offset: 4 |
| 10 | + access: Write |
| 11 | + fieldset: RSTCTL |
| 12 | + - name: STAT |
| 13 | + description: Status Register. |
| 14 | + byte_offset: 20 |
| 15 | + access: Read |
| 16 | + fieldset: STAT |
| 17 | +block/MATHACL: |
| 18 | + description: PERIPHERALREGION. |
| 19 | + items: |
| 20 | + - name: GPRCM |
| 21 | + array: |
| 22 | + len: 1 |
| 23 | + stride: 24 |
| 24 | + byte_offset: 2048 |
| 25 | + block: GPRCM |
| 26 | + - name: CTL |
| 27 | + description: Control Register. |
| 28 | + byte_offset: 4352 |
| 29 | + fieldset: CTL |
| 30 | + - name: OP2 |
| 31 | + description: Operand 2 register. |
| 32 | + byte_offset: 4376 |
| 33 | + fieldset: OP2 |
| 34 | + - name: OP1 |
| 35 | + description: Operand 1 register. |
| 36 | + byte_offset: 4380 |
| 37 | + fieldset: OP1 |
| 38 | + - name: RES1 |
| 39 | + description: Result 1 register. |
| 40 | + byte_offset: 4384 |
| 41 | + fieldset: RES1 |
| 42 | + - name: RES2 |
| 43 | + description: Result 2 register. |
| 44 | + byte_offset: 4388 |
| 45 | + fieldset: RES2 |
| 46 | + - name: STATUS |
| 47 | + description: Status Register. |
| 48 | + byte_offset: 4400 |
| 49 | + access: Read |
| 50 | + fieldset: STATUS |
| 51 | + - name: STATUSCLR |
| 52 | + description: Status flag clear register. |
| 53 | + byte_offset: 4416 |
| 54 | + access: Write |
| 55 | + fieldset: STATUSCLR |
| 56 | +fieldset/CTL: |
| 57 | + description: Control Register. |
| 58 | + fields: |
| 59 | + - name: FUNC |
| 60 | + description: ULP_ADCHP Enable Conversions. |
| 61 | + bit_offset: 0 |
| 62 | + bit_size: 5 |
| 63 | + enum: FUNC |
| 64 | + - name: OPTYPE |
| 65 | + description: Operand type, could signed or unsigned. applicable to DIV function. |
| 66 | + bit_offset: 5 |
| 67 | + bit_size: 1 |
| 68 | + - name: QVAL |
| 69 | + description: Indicates the fractional bits in the operands, ranges from 0 to 31. Applicable to DIV function. |
| 70 | + bit_offset: 8 |
| 71 | + bit_size: 5 |
| 72 | + enum: QVAL |
| 73 | + - name: SFACTOR |
| 74 | + description: Scaling factor. In case of SQRT function, the input operand needs to be in a range. If not it has to be scaled to 2^(+/-n). This field should be written with the value 'n'. |
| 75 | + bit_offset: 16 |
| 76 | + bit_size: 6 |
| 77 | + - name: SATEN |
| 78 | + description: Saturation enable This bit is shared among DIV, SQUARE32, MPY32, MAC and SAC functions. When enabled, it will make the result to saturate to maximum value in case of an overflow event When disabled, the result will overflow to an unknown value. |
| 79 | + bit_offset: 22 |
| 80 | + bit_size: 1 |
| 81 | + - name: NUMITER |
| 82 | + description: 'Number of iterations, applicable if the function does the computations iteratively, for example sine/cosine/atan2/sqrt. Note: A value of 0 is interpreted as 31.' |
| 83 | + bit_offset: 24 |
| 84 | + bit_size: 5 |
| 85 | +fieldset/OP1: |
| 86 | + description: Operand 1 register. |
| 87 | + fields: |
| 88 | + - name: DATA |
| 89 | + description: Operand 1 Register |
| 90 | + bit_offset: 0 |
| 91 | + bit_size: 32 |
| 92 | +fieldset/OP2: |
| 93 | + description: Operand 2 register. |
| 94 | + fields: |
| 95 | + - name: DATA |
| 96 | + description: Operand 1 Register |
| 97 | + bit_offset: 0 |
| 98 | + bit_size: 32 |
| 99 | +fieldset/PWREN: |
| 100 | + description: Power enable. |
| 101 | + fields: |
| 102 | + - name: ENABLE |
| 103 | + description: Enable the power. |
| 104 | + bit_offset: 0 |
| 105 | + bit_size: 1 |
| 106 | + - name: KEY |
| 107 | + description: KEY to allow Power State Change 26h = KEY to allow write access to this register |
| 108 | + bit_offset: 24 |
| 109 | + bit_size: 8 |
| 110 | + enum: PWREN_KEY |
| 111 | +fieldset/RES1: |
| 112 | + description: Result 1 register. |
| 113 | + fields: |
| 114 | + - name: DATA |
| 115 | + description: Result 1 Register |
| 116 | + bit_offset: 0 |
| 117 | + bit_size: 32 |
| 118 | +fieldset/RES2: |
| 119 | + description: Result 2 register. |
| 120 | + fields: |
| 121 | + - name: DATA |
| 122 | + description: Result 2 Register |
| 123 | + bit_offset: 0 |
| 124 | + bit_size: 32 |
| 125 | +fieldset/RSTCTL: |
| 126 | + description: Reset Control. |
| 127 | + fields: |
| 128 | + - name: RESETASSERT |
| 129 | + description: Assert reset to the peripheral. |
| 130 | + bit_offset: 0 |
| 131 | + bit_size: 1 |
| 132 | + enum: RESETASSERT |
| 133 | + - name: RESETSTKYCLR |
| 134 | + description: Clear the RESETSTKY bit in the STAT register. |
| 135 | + bit_offset: 1 |
| 136 | + bit_size: 1 |
| 137 | + enum: RESETSTKYCLR |
| 138 | + - name: KEY |
| 139 | + description: Unlock key B1h = KEY to allow write access to this register |
| 140 | + bit_offset: 24 |
| 141 | + bit_size: 8 |
| 142 | + enum: RESET_KEY |
| 143 | +fieldset/STAT: |
| 144 | + description: Status Register. |
| 145 | + fields: |
| 146 | + - name: RESETSTKY |
| 147 | + description: This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register. |
| 148 | + bit_offset: 16 |
| 149 | + bit_size: 1 |
| 150 | + enum: RESETSTKY |
| 151 | +fieldset/STATUS: |
| 152 | + description: Status Register. |
| 153 | + fields: |
| 154 | + - name: UF |
| 155 | + description: Underflow Flag. |
| 156 | + bit_offset: 0 |
| 157 | + bit_size: 1 |
| 158 | + - name: OVF |
| 159 | + description: Overflow bit for MPY32, SQUARE32, DIV, MAC, and SAC functions This bit will be set on overflow and will retain its value until cleared by writing 1 into CLR.CLR_OVF. |
| 160 | + bit_offset: 1 |
| 161 | + bit_size: 1 |
| 162 | + - name: ERR |
| 163 | + description: Incorrect inputs/outputs. |
| 164 | + bit_offset: 2 |
| 165 | + bit_size: 2 |
| 166 | + enum: ERR |
| 167 | + - name: BUSY |
| 168 | + description: MATHACL busy bit. |
| 169 | + bit_offset: 8 |
| 170 | + bit_size: 1 |
| 171 | + enum: BUSY |
| 172 | +fieldset/STATUSCLR: |
| 173 | + description: Status flag clear register. |
| 174 | + fields: |
| 175 | + - name: CLR_UF |
| 176 | + description: Write 1 to this bit to clear STATUS.UF bit. |
| 177 | + bit_offset: 0 |
| 178 | + bit_size: 1 |
| 179 | + - name: CLR_OVF |
| 180 | + description: Write 1 to this bit to clear STATUS.OVF bit. |
| 181 | + bit_offset: 1 |
| 182 | + bit_size: 1 |
| 183 | + - name: CLR_ERR |
| 184 | + description: Write 1 to this bit to clear STATUS.ERR field. |
| 185 | + bit_offset: 2 |
| 186 | + bit_size: 1 |
| 187 | +enum/BUSY: |
| 188 | + bit_size: 1 |
| 189 | + variants: |
| 190 | + - name: DONE |
| 191 | + description: Compute has completed. |
| 192 | + value: 0 |
| 193 | + - name: NOTDONE |
| 194 | + description: Compute ongoing. |
| 195 | + value: 1 |
| 196 | +enum/ERR: |
| 197 | + bit_size: 2 |
| 198 | + variants: |
| 199 | + - name: NOERROR |
| 200 | + description: No Error in computation. |
| 201 | + value: 0 |
| 202 | + - name: DIVBY0 |
| 203 | + description: DIVBY0 error. |
| 204 | + value: 1 |
| 205 | +enum/FUNC: |
| 206 | + bit_size: 5 |
| 207 | + variants: |
| 208 | + - name: NOP |
| 209 | + description: No operation. |
| 210 | + value: 0 |
| 211 | + - name: SINCOS |
| 212 | + description: Sine and Cosine operation. |
| 213 | + value: 1 |
| 214 | + - name: ATAN2 |
| 215 | + description: Arc tangent with x and y values as operands. |
| 216 | + value: 2 |
| 217 | + - name: DIV |
| 218 | + description: Divide, the operands are numerator, denominator, and the divide type. Result is the quotient and reminder. |
| 219 | + value: 4 |
| 220 | + - name: SQRT |
| 221 | + description: Do square root. Operand is the number whoose square root needs to be computed. The number if outside the range needs to be scaled up down by 2 power 2n to bring it with in the range. |
| 222 | + value: 5 |
| 223 | + - name: MPY32 |
| 224 | + description: 32-bit Multiply Result. |
| 225 | + value: 6 |
| 226 | + - name: SQUARE32 |
| 227 | + description: 32-bit square result. |
| 228 | + value: 7 |
| 229 | + - name: MPY64 |
| 230 | + description: 64-bit multiply result. |
| 231 | + value: 8 |
| 232 | + - name: SQUARE64 |
| 233 | + description: 64-bit multiply result. |
| 234 | + value: 9 |
| 235 | + - name: MAC |
| 236 | + description: Multiply and accumulate operation. |
| 237 | + value: 10 |
| 238 | + - name: SAC |
| 239 | + description: Square and accumulate operation. |
| 240 | + value: 11 |
| 241 | +enum/PWREN_KEY: |
| 242 | + bit_size: 8 |
| 243 | + variants: |
| 244 | + - name: KEY |
| 245 | + value: 38 |
| 246 | +enum/QVAL: |
| 247 | + bit_size: 5 |
| 248 | + variants: |
| 249 | + - name: Q0 |
| 250 | + description: Q0 operands. |
| 251 | + value: 0 |
| 252 | + - name: Q1 |
| 253 | + description: Q1 operands. |
| 254 | + value: 1 |
| 255 | + - name: Q2 |
| 256 | + description: Q2 operands. |
| 257 | + value: 2 |
| 258 | + - name: Q3 |
| 259 | + description: Q3 operands. |
| 260 | + value: 3 |
| 261 | + - name: Q4 |
| 262 | + description: Q4 operands. |
| 263 | + value: 4 |
| 264 | + - name: Q5 |
| 265 | + description: Q5 operands. |
| 266 | + value: 5 |
| 267 | + - name: Q6 |
| 268 | + description: Q6 operands. |
| 269 | + value: 6 |
| 270 | + - name: Q7 |
| 271 | + description: Q7 operands. |
| 272 | + value: 7 |
| 273 | + - name: Q8 |
| 274 | + description: Q8 operands. |
| 275 | + value: 8 |
| 276 | + - name: Q9 |
| 277 | + description: Q9 operands. |
| 278 | + value: 9 |
| 279 | + - name: Q10 |
| 280 | + description: Q10 operands. |
| 281 | + value: 10 |
| 282 | + - name: Q11 |
| 283 | + description: Q11 operands. |
| 284 | + value: 11 |
| 285 | + - name: Q12 |
| 286 | + description: Q12 operands. |
| 287 | + value: 12 |
| 288 | + - name: Q13 |
| 289 | + description: Q13 operands. |
| 290 | + value: 13 |
| 291 | + - name: Q14 |
| 292 | + description: Q14 operands. |
| 293 | + value: 14 |
| 294 | + - name: Q15 |
| 295 | + description: Q15 operands. |
| 296 | + value: 15 |
| 297 | + - name: Q16 |
| 298 | + description: Q16 operands. |
| 299 | + value: 16 |
| 300 | + - name: Q17 |
| 301 | + description: Q17 operands. |
| 302 | + value: 17 |
| 303 | + - name: Q18 |
| 304 | + description: Q18 operands. |
| 305 | + value: 18 |
| 306 | + - name: Q19 |
| 307 | + description: Q19 operands. |
| 308 | + value: 19 |
| 309 | + - name: Q20 |
| 310 | + description: Q20 operands. |
| 311 | + value: 20 |
| 312 | + - name: Q21 |
| 313 | + description: Q21 operands. |
| 314 | + value: 21 |
| 315 | + - name: Q22 |
| 316 | + description: Q22 operands. |
| 317 | + value: 22 |
| 318 | + - name: Q23 |
| 319 | + description: Q23 operands. |
| 320 | + value: 23 |
| 321 | + - name: Q24 |
| 322 | + description: Q24 operands. |
| 323 | + value: 24 |
| 324 | + - name: Q25 |
| 325 | + description: Q25 operands. |
| 326 | + value: 25 |
| 327 | + - name: Q26 |
| 328 | + description: Q26 operands. |
| 329 | + value: 26 |
| 330 | + - name: Q27 |
| 331 | + description: Q27 operands. |
| 332 | + value: 27 |
| 333 | + - name: Q28 |
| 334 | + description: Q28 operands. |
| 335 | + value: 28 |
| 336 | + - name: Q29 |
| 337 | + description: Q29 operands. |
| 338 | + value: 29 |
| 339 | + - name: Q30 |
| 340 | + description: Q30 operands. |
| 341 | + value: 30 |
| 342 | + - name: Q31 |
| 343 | + description: Q31 operands. |
| 344 | + value: 31 |
| 345 | +enum/RESETASSERT: |
| 346 | + bit_size: 1 |
| 347 | + variants: |
| 348 | + - name: NOP |
| 349 | + description: Writing 0 has no effect. |
| 350 | + value: 0 |
| 351 | + - name: ASSERT |
| 352 | + description: Assert reset. |
| 353 | + value: 1 |
| 354 | +enum/RESETSTKY: |
| 355 | + bit_size: 1 |
| 356 | + variants: |
| 357 | + - name: NORES |
| 358 | + description: The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register. |
| 359 | + value: 0 |
| 360 | + - name: RESET |
| 361 | + description: The peripheral was reset since the last bit clear. |
| 362 | + value: 1 |
| 363 | +enum/RESETSTKYCLR: |
| 364 | + bit_size: 1 |
| 365 | + variants: |
| 366 | + - name: NOP |
| 367 | + description: Writing 0 has no effect. |
| 368 | + value: 0 |
| 369 | + - name: CLR |
| 370 | + description: Clear reset sticky bit. |
| 371 | + value: 1 |
| 372 | +enum/RESET_KEY: |
| 373 | + bit_size: 8 |
| 374 | + variants: |
| 375 | + - name: KEY |
| 376 | + value: 177 |
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