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WWDT: finalize generation (#10)
* WWDT: extend YAML transform config * WWDT: add code generation & cleanup - transofrm YAML config cleanup - add some helper write keys to the code generation - add wwwt to the perimap.rs & peripheral.rs
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‎data/registers/wwdt_v1.yaml‎

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block/CPU_INT:
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items:
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- name: IIDX
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description: Interrupt index.
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byte_offset: 0
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access: Read
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fieldset: IIDX
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- name: IMASK
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description: Interrupt mask.
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byte_offset: 8
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fieldset: INT
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- name: RIS
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description: Raw interrupt status.
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byte_offset: 16
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access: Read
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fieldset: INT
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- name: MIS
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description: Masked interrupt status.
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byte_offset: 24
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access: Read
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fieldset: INT
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- name: ISET
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description: Interrupt set.
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byte_offset: 32
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access: Write
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fieldset: INT
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- name: ICLR
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description: Interrupt clear.
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byte_offset: 40
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access: Write
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fieldset: INT
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block/GPRCM:
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items:
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- name: PWREN
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description: Power enable.
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byte_offset: 0
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fieldset: PWREN
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- name: RSTCTL
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description: Reset Control.
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byte_offset: 4
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access: Write
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fieldset: RSTCTL
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- name: STAT
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description: Status Register.
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byte_offset: 20
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access: Read
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fieldset: STAT
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block/WWDT:
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description: WWDT.
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items:
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- name: GPRCM
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array:
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len: 1
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stride: 24
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byte_offset: 2048
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block: GPRCM
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- name: PDBGCTL
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description: Peripheral Debug Control.
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byte_offset: 4120
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fieldset: PDBGCTL
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- name: CPU_INT
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array:
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len: 1
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stride: 44
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byte_offset: 4128
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block: CPU_INT
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- name: EVT_MODE
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description: Event Mode.
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byte_offset: 4320
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fieldset: EVT_MODE
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- name: DESC
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description: Module Description.
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byte_offset: 4348
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access: Read
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fieldset: DESC
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- name: WWDTCTL0
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description: Window Watchdog Timer Control Register 0.
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byte_offset: 4352
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fieldset: WWDTCTL0
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- name: WWDTCTL1
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description: Window Watchdog Timer Control Register 0.
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byte_offset: 4356
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fieldset: WWDTCTL1
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- name: WWDTCNTRST
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description: Window Watchdog Timer Counter Reset Register.
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byte_offset: 4360
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fieldset: WWDTCNTRST
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- name: WWDTSTAT
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description: Window Watchdog Timer Status Register.
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byte_offset: 4364
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access: Read
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fieldset: WWDTSTAT
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fieldset/DESC:
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description: Module Description.
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fields:
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- name: MINREV
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description: Minor rev of the IP.
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bit_offset: 0
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bit_size: 4
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- name: MAJREV
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description: Major rev of the IP.
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bit_offset: 4
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bit_size: 4
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- name: INSTNUM
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description: Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances.
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bit_offset: 8
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bit_size: 4
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- name: FEATUREVER
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description: Feature Set for the module *instance*.
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bit_offset: 12
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bit_size: 4
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- name: MODULEID
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description: Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
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bit_offset: 16
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bit_size: 16
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fieldset/EVT_MODE:
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description: Event Mode.
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fields:
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- name: INT0_CFG
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description: Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0].
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bit_offset: 0
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bit_size: 2
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enum: INT_CFG
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fieldset/IIDX:
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description: Interrupt index.
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fields:
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- name: STAT
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description: Module Interrupt Vector Value. This register provides the highest priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC.
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bit_offset: 0
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bit_size: 5
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enum: STAT
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fieldset/INT:
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description: Interrupt clear.
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fields:
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- name: INTTIM
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description: Interval Timer Interrupt.
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bit_offset: 0
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bit_size: 1
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fieldset/PDBGCTL:
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description: Peripheral Debug Control.
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fields:
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- name: FREE
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description: Free run control.
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bit_offset: 0
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bit_size: 1
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fieldset/PWREN:
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description: Power enable.
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fields:
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- name: ENABLE
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description: 'Enable the power Note: For safety devices the power cannot be disabled once enabled.'
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bit_offset: 0
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bit_size: 1
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- name: KEY
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description: KEY to allow Power State Change 26h = KEY to allow write access to this register
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bit_offset: 24
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bit_size: 8
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enum: PWREN_KEY
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fieldset/RSTCTL:
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description: Reset Control.
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fields:
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- name: RESETASSERT
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description: 'Assert reset to the peripheral Note: For safety devices a watchdog reset by software is not possible.'
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bit_offset: 0
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bit_size: 1
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- name: RESETSTKYCLR
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description: Clear [GPRCM.STAT.RESETSTKY].
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bit_offset: 1
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bit_size: 1
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- name: KEY
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description: Unlock key B1h = KEY to allow write access to this register
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bit_offset: 24
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bit_size: 8
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enum: RESET_KEY
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fieldset/STAT:
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description: Status Register.
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fields:
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- name: RESETSTKY
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description: This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register.
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bit_offset: 16
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bit_size: 1
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fieldset/WWDTCNTRST:
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description: Window Watchdog Timer Counter Reset Register.
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fields:
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- name: RESTART
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description: Window Watchdog Timer Counter Restart Writing 00A7h to this register restarts the WWDT Counter.
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bit_offset: 0
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bit_size: 32
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enum: WWDTCNTRST_RESTART
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fieldset/WWDTCTL0:
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description: Window Watchdog Timer Control Register 0.
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fields:
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- name: CLKDIV
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description: Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0.
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bit_offset: 0
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bit_size: 3
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- name: PER
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description: Timer Period of the WWDT. These bits select the total watchdog timer count.
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bit_offset: 4
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bit_size: 3
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enum: PER
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- name: WINDOW0
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description: Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1).
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bit_offset: 8
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bit_size: 3
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enum: WINDOW
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- name: WINDOW1
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description: Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1).
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bit_offset: 12
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bit_size: 3
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enum: WINDOW
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- name: MODE
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description: Window Watchdog Timer Mode.
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bit_offset: 16
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bit_size: 1
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enum: MODE
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- name: STISM
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description: 'Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported.'
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bit_offset: 17
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bit_size: 1
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enum: STISM
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- name: KEY
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description: KEY to allow write access to WWDTCTL0 = C9h.
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bit_offset: 24
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bit_size: 8
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enum: WWDTCTL0_KEY
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fieldset/WWDTCTL1:
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description: Window Watchdog Timer Control Register 0.
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fields:
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- name: WINSEL
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description: Close Window Select.
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bit_offset: 0
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bit_size: 1
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enum: WINSEL
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- name: KEY
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description: KEY to allow write access to WWDTCTL1 = BEh.
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bit_offset: 24
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bit_size: 8
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enum: WWDTCTL1_KEY
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fieldset/WWDTSTAT:
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description: Window Watchdog Timer Status Register.
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fields:
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- name: RUN
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description: Watchdog running status flag.
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bit_offset: 0
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bit_size: 1
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enum/INT_CFG:
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bit_size: 2
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variants:
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- name: DISABLE
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description: The interrupt or event line is disabled.
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value: 0
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- name: SOFTWARE
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description: The interrupt or event line is in software mode. Software must clear the RIS.
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value: 1
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- name: HARDWARE
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description: The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
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value: 2
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enum/MODE:
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bit_size: 1
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variants:
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- name: WINDOW
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description: 'Window Watchdog Timer Mode. The WWDT will generate a error signal to the ESM when following conditions occur: - Timer Expiration (Timeout) - Reset WWDT during the active window closed period - Keyword violation.'
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value: 0
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- name: INTERVAL
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description: Interval Timer Mode. The WWDT acts as an interval timer. It generates an interrupt on timeout.
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value: 1
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enum/PER:
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bit_size: 3
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variants:
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- name: EN_25
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description: Total timer count is 2^25.
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value: 0
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- name: EN_21
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description: Total timer count is 2^21.
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value: 1
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- name: EN_18
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description: Total timer count is 2^18.
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value: 2
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- name: EN_15
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description: Total timer count is 2^15.
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value: 3
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- name: EN_12
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description: Total timer count is 2^12 (default).
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value: 4
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- name: EN_10
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description: Total timer count is 2^10.
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value: 5
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- name: EN_8
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description: Total timer count is 2^8.
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value: 6
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- name: EN_6
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description: Total timer count is 2^6.
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value: 7
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enum/PWREN_KEY:
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bit_size: 8
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variants:
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- name: KEY
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value: 38
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enum/RESET_KEY:
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bit_size: 8
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variants:
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- name: KEY
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value: 177
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enum/STAT:
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bit_size: 5
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variants:
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- name: NO_INTR
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description: No interrupt pending.
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value: 0
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- name: INTTIM
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description: 'Interval Timer Interrupt; Interrupt Flag: INTTIM; Interrupt Priority: Highest.'
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value: 1
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enum/STISM:
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bit_size: 1
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variants:
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- name: CONT
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description: The WWDT continues to function in Sleep mode.
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value: 0
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- name: STOP
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description: The WWDT stops in Sleep mode and resumes where it was stopped after wakeup.
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value: 1
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enum/WINDOW:
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bit_size: 3
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variants:
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- name: SIZE_0
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description: 0% (No closed Window).
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value: 0
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- name: SIZE_12
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description: 12.50% of the total timer period is closed window.
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value: 1
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- name: SIZE_18
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description: 18.75% of the total timer period is closed window.
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value: 2
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- name: SIZE_25
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description: 25% of the total timer period is closed window.
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value: 3
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- name: SIZE_50
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description: 50% of the total timer period is closed window.
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value: 4
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- name: SIZE_75
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description: 75% of the total timer period is closed window.
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value: 5
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- name: SIZE_81
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description: 81.25% of the total timer period is closed window.
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value: 6
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- name: SIZE_87
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description: 87.50% of the total timer period is closed window.
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value: 7
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enum/WINSEL:
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bit_size: 1
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variants:
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- name: WIN0
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description: In window mode field WINDOW0 of WDDTCTL0 defines the closed window size.
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value: 0
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- name: WIN1
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description: In window mode field WINDOW1 of WDDTCTL0 defines the closed window size.
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value: 1
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enum/WWDTCNTRST_RESTART:
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bit_size: 32
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variants:
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- name: RESTART
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value: 167
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enum/WWDTCTL0_KEY:
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bit_size: 8
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variants:
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- name: KEY
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value: 201
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enum/WWDTCTL1_KEY:
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bit_size: 8
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variants:
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- name: KEY
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value: 190

‎mspm0-data-gen/src/perimap.rs‎

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@@ -10,6 +10,7 @@ pub static PERIMAP: RegexMap<&str> = RegexMap::new(&[
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(".*:iomux", "v1"),
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(".*:tim", "v1"),
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(".*:adc", "v1"),
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(".*:wwdt", "v1"),
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("mspm0c110x:sysctl", "c110x"),
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("msps003fx:sysctl", "c110x"),
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("mspm0g..0x:sysctl", "g350x_g310x_g150x_g110x"),

‎mspm0-metapac-gen/src/peripheral.rs‎

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@@ -18,6 +18,7 @@ const GENERATE_PERIPHERALS: &[PeripheralType] = &[
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PeripheralType::Sysctl,
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PeripheralType::Tim,
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PeripheralType::Uart,
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PeripheralType::Wwdt,
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];
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pub fn generate(chip: &Chip, all_versions: &mut BTreeMap<String, BTreeSet<String>>) -> TokenStream {

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