clk: tegra: Add library for the DFLL clock source (open-loop mode)

Add shared code to support the Tegra DFLL clocksource in open-loop
mode. This root clocksource is present on the Tegra124 SoCs. The
DFLL is the intended primary clock source for the fast CPU cluster.

This code is very closely based on a patch by Paul Walmsley from
December (http://comments.gmane.org/gmane.linux.ports.tegra/15273),
which in turn comes from the internal driver by originally created
by Aleksandr Frid <[email protected]>.

Subsequent patches will add support for closed loop mode and drivers
for the Tegra124 fast CPU cluster DFLL devices, which rely on this
code.

Signed-off-by: Paul Walmsley <[email protected]>
Signed-off-by: Tuomas Tynkkynen <[email protected]>
Signed-off-by: Mikko Perttunen <[email protected]>
Acked-by: Peter De Schrijver <[email protected]>
Acked-by: Michael Turquette <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>

Author: dezgeg

drivers/clk/tegra/Makefile

@@ -1,5 +1,6 @@
 obj-y					+= clk.o
 obj-y					+= clk-audio-sync.o
+obj-y					+= clk-dfll.o
 obj-y					+= clk-divider.o
 obj-y					+= clk-periph.o
 obj-y					+= clk-periph-gate.o