feat: Remove support for 64-cell accesses (#1466)

Author: zlangley

crates/vm/src/arch/config.rs

@@ -56,7 +56,7 @@ pub struct MemoryConfig {
 
 impl Default for MemoryConfig {
     fn default() -> Self {
-        Self::new(3, 1, 29, 29, 17, 64, 1 << 24)
+        Self::new(3, 1, 29, 29, 17, 32, 1 << 24)
     }
 }
 

crates/vm/src/system/memory/adapter/mod.rs

@@ -43,13 +43,13 @@ impl<F> AccessAdapterInventory<F> {
         let mb = memory_bus;
         let cmb = clk_max_bits;
         let maan = max_access_adapter_n;
+        assert!(matches!(maan, 2 | 4 | 8 | 16 | 32));
         let chips: Vec<_> = [
             Self::create_access_adapter_chip::<2>(rc.clone(), mb, cmb, maan),
             Self::create_access_adapter_chip::<4>(rc.clone(), mb, cmb, maan),
             Self::create_access_adapter_chip::<8>(rc.clone(), mb, cmb, maan),
             Self::create_access_adapter_chip::<16>(rc.clone(), mb, cmb, maan),
             Self::create_access_adapter_chip::<32>(rc.clone(), mb, cmb, maan),
-            Self::create_access_adapter_chip::<64>(rc.clone(), mb, cmb, maan),
         ]
         .into_iter()
         .flatten()
@@ -184,7 +184,6 @@ enum GenericAccessAdapterChip<F> {
     N8(AccessAdapterChip<F, 8>),
     N16(AccessAdapterChip<F, 16>),
     N32(AccessAdapterChip<F, 32>),
-    N64(AccessAdapterChip<F, 64>),
 }
 
 impl<F> GenericAccessAdapterChip<F> {
@@ -202,8 +201,7 @@ impl<F> GenericAccessAdapterChip<F> {
             8 => GenericAccessAdapterChip::N8(AccessAdapterChip::new(rc, mb, cmb)),
             16 => GenericAccessAdapterChip::N16(AccessAdapterChip::new(rc, mb, cmb)),
             32 => GenericAccessAdapterChip::N32(AccessAdapterChip::new(rc, mb, cmb)),
-            64 => GenericAccessAdapterChip::N64(AccessAdapterChip::new(rc, mb, cmb)),
-            _ => panic!("Only supports N in (2, 4, 8, 16, 32, 64)"),
+            _ => panic!("Only supports N in (2, 4, 8, 16, 32)"),
         }
     }
 
@@ -215,7 +213,6 @@ impl<F> GenericAccessAdapterChip<F> {
             GenericAccessAdapterChip::N8(chip) => &chip.records,
             GenericAccessAdapterChip::N16(chip) => &chip.records,
             GenericAccessAdapterChip::N32(chip) => &chip.records,
-            GenericAccessAdapterChip::N64(chip) => &chip.records,
         }
     }
 }

crates/vm/src/system/memory/tests.rs

@@ -43,7 +43,7 @@ use crate::{
     },
 };
 
-const MAX: usize = 64;
+const MAX: usize = 32;
 const RANGE_CHECKER_BUS: BusIndex = 3;
 
 #[repr(C)]

crates/vm/tests/integration_test.rs

@@ -321,7 +321,7 @@ fn test_vm_initial_memory() {
 fn test_vm_1_persistent() {
     let engine = BabyBearPoseidon2Engine::new(FriParameters::standard_fast());
     let config = NativeConfig {
-        system: SystemConfig::new(3, MemoryConfig::new(2, 1, 16, 29, 15, 64, 1024), 0),
+        system: SystemConfig::new(3, MemoryConfig::new(2, 1, 16, 29, 15, 32, 1024), 0),
         native: Default::default(),
     }
     .with_continuations();
@@ -587,15 +587,15 @@ fn test_vm_max_access_adapter_8() {
         config.system.memory_config.max_access_adapter_n = 8;
         let chip_complex2 = config.create_chip_complex().unwrap();
         let mem_ctrl2 = chip_complex2.base.memory_controller;
-        // AccessAdapterAir with N=16/32/64 are disabled.
-        assert_eq!(mem_ctrl1.air_names().len(), mem_ctrl2.air_names().len() + 3);
+        // AccessAdapterAir with N=16/32 are disabled.
+        assert_eq!(mem_ctrl1.air_names().len(), mem_ctrl2.air_names().len() + 2);
         assert_eq!(
             mem_ctrl1.airs::<BabyBearPoseidon2Config>().len(),
-            mem_ctrl2.airs::<BabyBearPoseidon2Config>().len() + 3
+            mem_ctrl2.airs::<BabyBearPoseidon2Config>().len() + 2
         );
         assert_eq!(
             mem_ctrl1.current_trace_heights().len(),
-            mem_ctrl2.current_trace_heights().len() + 3
+            mem_ctrl2.current_trace_heights().len() + 2
         );
     }
     air_test(config, program);
@@ -622,7 +622,7 @@ fn test_vm_field_extension_arithmetic_persistent() {
 
     let program = Program::from_instructions(&instructions);
     let config = NativeConfig {
-        system: SystemConfig::new(3, MemoryConfig::new(2, 1, 16, 29, 15, 64, 1024), 0)
+        system: SystemConfig::new(3, MemoryConfig::new(2, 1, 16, 29, 15, 32, 1024), 0)
             .with_continuations(),
         native: Default::default(),
     };

docs/specs/ISA.md

@@ -133,7 +133,7 @@ to. Address space `0` is considered a read-only array with `[a]_0 = a` for any `
 #### Memory Accesses and Block Accesses
 
 VM instructions can access (read or write) a contiguous list of cells (called a **block**) in a single address space.
-The block size must be in the set `{1, 2, 4, 8, 16, 32, 64}`, and the access does not need to be aligned, meaning that
+The block size must be in the set `{1, 2, 4, 8, 16, 32}`, and the access does not need to be aligned, meaning that
 it can start from any pointer address, even those not divisible by the block size. An access is called a **block access
 ** if it has size greater than 1. Block accesses are not supported for address space `0`.