mtd: rawnand: denali_dt: set clk_x_rate to 200 MHz unconditionally

Since commit 1bb8866 ("mtd: nand: denali: handle timing parameters
by setup_data_interface()"), denali_dt.c gets the clock rate from the
clock driver.  The driver expects the frequency of the bus interface
clock, whereas the clock driver of SOCFPGA provides the core clock.
Thus, the setup_data_interface() hook calculates timing parameters
based on a wrong frequency.

To make it work without relying on the clock driver, hard-code the clock
frequency, 200MHz.  This is fine for existing DT of UniPhier, and also
fixes the issue of SOCFPGA because both platforms use 200 MHz for the
bus interface clock.

Fixes: 1bb8866 ("mtd: nand: denali: handle timing parameters by setup_data_interface()")
Cc: linux-stable <[email protected]> #4.14+
Reported-by: Philipp Rosenberger <[email protected]>
Suggested-by: Boris Brezillon <[email protected]>
Signed-off-by: Masahiro Yamada <[email protected]>
Tested-by: Richard Weinberger <[email protected]>
Signed-off-by: Boris Brezillon <[email protected]>

Author: masahir0y

drivers/mtd/nand/raw/denali_dt.c

@@ -123,7 +123,11 @@ static int denali_dt_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
-	denali->clk_x_rate = clk_get_rate(dt->clk);
+	/*
+	 * Hardcode the clock rate for the backward compatibility.
+	 * This works for both SOCFPGA and UniPhier.
+	 */
+	denali->clk_x_rate = 200000000;
 
 	ret = denali_init(denali);
 	if (ret)