Merge pull request #9 from rust-embedded/rename-crate

Renamed cortex-r to cortex-ar

Author: jonathanpallant

.github/workflows/build.yml

@@ -36,7 +36,7 @@ jobs:
     runs-on: ubuntu-24.04
     strategy:
       matrix:
-        rust: [stable, 1.82]
+        rust: [stable, 1.59]
     steps:
       - name: Checkout
         uses: actions/checkout@v4
@@ -231,7 +231,7 @@ jobs:
           rustup default stable
       - name: Run cargo test
         run: |
-          cargo test --manifest-path cortex-r/Cargo.toml
+          cargo test --manifest-path cortex-ar/Cargo.toml
 
   # Run some programs in QEMU
   qemu-test:

Cargo.toml

@@ -3,7 +3,7 @@ exclude = [
   "arm-targets",
 ]
 members = [
-  "cortex-r",
+  "cortex-ar",
   "cortex-r-examples",
   "cortex-r-rt",
 ]

LICENSE-MIT

@@ -1,5 +1,5 @@
-Copyright (c) The Cortex-R Crate Developers
 Copyright (c) Ferrous Systems
+Copyright (c) The Rust Embedded Devices Working Group developers
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

README.md

@@ -1,12 +1,16 @@
 [package]
-authors = ["Jonathan Pallant <[email protected]>", "The Cortex-R Team <[email protected]>"]
+authors = [
+    "Jonathan Pallant <[email protected]>",
+    "The Cortex-R Team <[email protected]>"
+]
+categories = ["development-tools::build-utils"]
 description = "Compile-time feature detection for Arm processors"
 edition = "2021"
 license = "MIT OR Apache-2.0"
 name = "arm-targets"
 readme = "README.md"
 repository = "https://github.com/rust-embedded/cortex-r.git"
-rust-version = "1.82"
+rust-version = "1.59"
 version = "0.1.0"
 
 [dependencies]

arm-targets/Cargo.toml

@@ -1,9 +1,24 @@
 [package]
-authors = ["Jonathan Pallant <[email protected]>", "The Cortex-R Team <[email protected]>"]
-description = "CPU support for Arm Cortex-R"
+authors = [
+    "Jonathan Pallant <[email protected]>",
+    "The Cortex-R Team <[email protected]>",
+]
+categories = [
+    "embedded",
+    "no-std",
+]
+description = "CPU support for AArch32 Arm Cortex-R and Arm Cortex-A"
 edition = "2021"
+keywords = [
+    "arm",
+    "cortex-a",
+    "cortex-r",
+    "embedded",
+    "no_std",
+    "no-std",
+]
 license = "MIT OR Apache-2.0"
-name = "cortex-r"
+name = "cortex-ar"
 readme = "README.md"
 repository = "https://github.com/rust-embedded/cortex-r.git"
 rust-version = "1.82"

cortex-r/Cargo.toml renamed to cortex-ar/Cargo.toml

@@ -6,7 +6,7 @@ use crate::register;
 ///
 /// Note that for most of these APIs to work, EL0 needs to have been granted
 /// access using methods like
-/// [El2GenericTimer::el0_access_physical_counter](crate::generic_timer::El2GenericTimer::el0_access_physical_counter).
+/// [El1PhysicalTimer::el0_access_physical_counter](crate::generic_timer::El1PhysicalTimer::el0_access_physical_counter).
 pub struct El0PhysicalTimer();
 
 impl El0PhysicalTimer {

cortex-ar/README.md

@@ -12,7 +12,7 @@ version = "0.1.0"
 
 [dependencies]
 arm-gic = {git = "https://github.com/google/arm-gic.git", rev = "46a8fc1720f5c28fccf4dfb5953b88dab7012e9c", optional = true}
-cortex-r = {path = "../cortex-r", features = ["critical-section-single-core"]}
+cortex-ar = {path = "../cortex-ar", features = ["critical-section-single-core"]}
 cortex-r-rt = {path = "../cortex-r-rt"}
 semihosting = {version = "0.1.18", features = ["stdio"]}
 

cortex-r/build.rs renamed to cortex-ar/build.rs

@@ -26,8 +26,8 @@ fn main() {
 /// Let's test some timers!
 #[cfg(arm_architecture = "v8-r")]
 fn main() {
-    use cortex_r::generic_timer::{El1PhysicalTimer, El1VirtualTimer, GenericTimer};
-    let cntfrq = cortex_r::register::Cntfrq::read().0;
+    use cortex_ar::generic_timer::{El1PhysicalTimer, El1VirtualTimer, GenericTimer};
+    let cntfrq = cortex_ar::register::Cntfrq::read().0;
     println!("cntfrq = {:.03} MHz", cntfrq as f32 / 1_000_000.0);
 
     let delay_ticks = cntfrq * 2;

cortex-r/src/asm.rs renamed to cortex-ar/src/asm.rs

@@ -4,7 +4,7 @@
 #![no_main]
 
 // pull in our start-up code
-use cortex_r as _;
+use cortex_ar as _;
 use cortex_r_examples as _;
 
 use arm_gic::{
@@ -33,7 +33,7 @@ const GICD_BASE_OFFSET: usize = 0x0000_0000usize;
 const GICR_BASE_OFFSET: usize = 0x0010_0000usize;
 
 fn dump_cpsr() {
-    let cpsr = cortex_r::register::Cpsr::read();
+    let cpsr = cortex_ar::register::Cpsr::read();
     println!("CPSR: {:?}", cpsr);
 }
 
@@ -42,7 +42,7 @@ fn dump_cpsr() {
 /// Called by [`kmain`].
 fn main() -> Result<(), core::fmt::Error> {
     // Get the GIC address by reading CBAR
-    let periphbase = cortex_r::register::ImpCbar::read().periphbase();
+    let periphbase = cortex_ar::register::ImpCbar::read().periphbase();
     println!("Found PERIPHBASE {:010p}", periphbase);
     let gicd_base = periphbase.wrapping_byte_add(GICD_BASE_OFFSET);
     let gicr_base = periphbase.wrapping_byte_add(GICR_BASE_OFFSET);
@@ -70,7 +70,7 @@ fn main() -> Result<(), core::fmt::Error> {
     println!("Enabling interrupts...");
     dump_cpsr();
     unsafe {
-        cortex_r::interrupt::enable();
+        cortex_ar::interrupt::enable();
     }
     dump_cpsr();
 
@@ -87,7 +87,7 @@ fn main() -> Result<(), core::fmt::Error> {
     );
 
     for _ in 0..1_000_000 {
-        cortex_r::asm::nop();
+        cortex_ar::asm::nop();
     }
 
     Ok(())

cortex-r/src/critical_section.rs renamed to cortex-ar/src/critical_section.rs

@@ -4,7 +4,7 @@
 #![no_main]
 
 // pull in our start-up code
-use cortex_r as _;
+use cortex_ar as _;
 use cortex_r_examples as _;
 
 use semihosting::println;

cortex-r/src/generic_timer/el0.rs renamed to cortex-ar/src/generic_timer/el0.rs

@@ -4,7 +4,7 @@
 #![no_main]
 
 // pull in our start-up code
-use cortex_r as _;
+use cortex_ar as _;
 use cortex_r_examples as _;
 
 use semihosting::println;
@@ -24,20 +24,20 @@ pub extern "C" fn kmain() {
 }
 
 fn chip_info() {
-    println!("{:?}", cortex_r::register::Midr::read());
-    println!("{:?}", cortex_r::register::Cpsr::read());
+    println!("{:?}", cortex_ar::register::Midr::read());
+    println!("{:?}", cortex_ar::register::Cpsr::read());
     #[cfg(arm_architecture = "v8-r")]
     {
-        println!("{:?}", cortex_r::register::ImpCbar::read());
-        println!("{:?}", cortex_r::register::Vbar::read());
+        println!("{:?}", cortex_ar::register::ImpCbar::read());
+        println!("{:?}", cortex_ar::register::Vbar::read());
         // This only works in EL2 and start-up put us in EL1
-        // println!("{:?}", cortex_r::register::Hvbar::read());
+        // println!("{:?}", cortex_ar::register::Hvbar::read());
     }
 }
 
 #[cfg(arm_architecture = "v7-r")]
 fn mpu_pmsa_v7() {
-    use cortex_r::{
+    use cortex_ar::{
         pmsav7::{CacheablePolicy, Config, MemAttr, Mpu, Region, RegionSize},
         register::Mpuir,
     };
@@ -90,7 +90,7 @@ fn mpu_pmsa_v7() {
 
 #[cfg(arm_architecture = "v8-r")]
 fn mpu_pmsa_v8() {
-    use cortex_r::{
+    use cortex_ar::{
         pmsav8::{
             AccessPerms, Cacheable, Config, El1Mpu, MemAttr, Region, RwAllocPolicy, Shareability,
         },
@@ -140,12 +140,12 @@ fn mpu_pmsa_v8() {
 fn test_changing_sctlr() {
     println!(
         "{:?} before setting C, I and Z",
-        cortex_r::register::Sctlr::read()
+        cortex_ar::register::Sctlr::read()
     );
-    cortex_r::register::Sctlr::modify(|w| {
+    cortex_ar::register::Sctlr::modify(|w| {
         w.set_c(true);
         w.set_i(true);
         w.set_z(true);
     });
-    println!("{:?} after", cortex_r::register::Sctlr::read());
+    println!("{:?} after", cortex_ar::register::Sctlr::read());
 }

cortex-r/src/generic_timer/el1.rs renamed to cortex-ar/src/generic_timer/el1.rs

@@ -4,7 +4,7 @@
 #![no_main]
 
 // pull in our start-up code
-use cortex_r as _;
+use cortex_ar as _;
 use cortex_r_examples as _;
 
 use semihosting::println;
@@ -27,7 +27,7 @@ fn main() -> Result<(), core::fmt::Error> {
     let y = x + 1;
     let z = (y as f64) * 1.5;
     println!("x = {}, y = {}, z = {:0.3}", x, y, z);
-    cortex_r::svc!(0xABCDEF);
+    cortex_ar::svc!(0xABCDEF);
     println!("x = {}, y = {}, z = {:0.3}", x, y, z);
     panic!("I am an example panic");
 }
@@ -38,6 +38,6 @@ unsafe extern "C" fn _svc_handler(arg: u32) {
     println!("In _svc_handler, with arg={:#06x}", arg);
     if arg == 0xABCDEF {
         // test nested SVC calls
-        cortex_r::svc!(0x456789);
+        cortex_ar::svc!(0x456789);
     }
 }

cortex-r/src/generic_timer/el2.rs renamed to cortex-ar/src/generic_timer/el2.rs

@@ -1,7 +1,22 @@
 [package]
-authors = ["Jonathan Pallant <[email protected]>", "The Cortex-R Team <[email protected]>"]
+authors = [
+    "Jonathan Pallant <[email protected]>",
+    "The Cortex-R Team <[email protected]>"
+]
+categories = [
+    "embedded",
+    "no-std",
+]
 description = "Run-time support for Arm Cortex-R"
 edition = "2021"
+keywords = [
+    "arm",
+    "cortex-r",
+    "embedded",
+    "no_std",
+    "no-std",
+    "run-time",
+]
 license = "MIT OR Apache-2.0"
 name = "cortex-r-rt"
 readme = "README.md"
@@ -10,7 +25,7 @@ rust-version = "1.82"
 version = "0.1.0"
 
 [dependencies]
-cortex-r = {version = "0.1.0", path = "../cortex-r"}
+cortex-ar = {version = "0.1.0", path = "../cortex-ar"}
 semihosting = {version = "0.1.18", features = ["stdio"]}
 
 [features]

cortex-r/src/generic_timer/mod.rs renamed to cortex-ar/src/generic_timer/mod.rs

@@ -85,10 +85,10 @@
 
 #![no_std]
 
-use cortex_r::register::{cpsr::ProcessorMode, Cpsr};
+use cortex_ar::register::{cpsr::ProcessorMode, Cpsr};
 
 #[cfg(arm_architecture = "v8-r")]
-use cortex_r::register::Hactlr;
+use cortex_ar::register::Hactlr;
 
 /// Our default exception handler.
 ///
@@ -424,7 +424,7 @@ core::arch::global_asm!(
             .raw_value()
     },
     te_bit = const {
-        cortex_r::register::Sctlr::new_with_raw_value(0)
+        cortex_ar::register::Sctlr::new_with_raw_value(0)
             .with_te(true)
             .raw_value()
     }