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use ConstZero instead of Default
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‎.github/workflows/ci.yml

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
on:
22
push:
3-
branches: master
3+
branches: [master]
44
pull_request:
55
merge_group:
66

‎CHANGELOG.md

+1
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/).
77

88
## [Unreleased]
99

10+
- *breaking change* use `ConstZero::ZERO` instead of `Default::default()` to force const
1011
- Add `mtvec_align` field to `riscv_config` to configure the byte alignment of interrupt vector table.
1112
- Fix reexport path when "%s" inside "derivedFrom"
1213
- Force using rust edition 2021 in CI

‎ci/script.sh

+1
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,7 @@ main() {
4343
echo 'cortex-m = "0.7.7"' >> $td/Cargo.toml
4444
echo 'cortex-m-rt = "0.7.3"' >> $td/Cargo.toml
4545
echo 'vcell = "0.1.3"' >> $td/Cargo.toml
46+
echo 'num-traits = { version = "0.2.19", default-features = false }' >> $td/Cargo.toml
4647
if [[ "$options" == *"--atomics"* ]]; then
4748
echo 'portable-atomic = { version = "1.4", default-features = false }' >> $td/Cargo.toml
4849
fi

‎ci/svd2rust-regress/src/svd_test.rs

+1
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@ use std::{
1313

1414
const CRATES_ALL: &[&str] = &[
1515
"critical-section = {version = \"1.0\", optional = true}",
16+
"num-traits = { version = \"0.2.19\", default-features = false }",
1617
"vcell = \"0.1.2\"",
1718
];
1819
const CRATES_MSP430: &[&str] = &["msp430 = \"0.4.0\"", "msp430-rt = \"0.4.0\""];

‎src/generate/generic.rs

+25-24
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,11 @@
11
use core::marker;
2+
use num_traits::{ConstOne, ConstZero};
23

34
/// Raw register type (`u8`, `u16`, `u32`, ...)
45
pub trait RawReg:
56
Copy
6-
+ Default
7+
+ ConstOne
8+
+ ConstZero
79
+ From<bool>
810
+ core::ops::BitOr<Output = Self>
911
+ core::ops::BitAnd<Output = Self>
@@ -14,8 +16,6 @@ pub trait RawReg:
1416
{
1517
/// Mask for bits of width `WI`
1618
fn mask<const WI: u8>() -> Self;
17-
/// Mask for bits of width 1
18-
fn one() -> Self;
1919
}
2020

2121
macro_rules! raw_reg {
@@ -25,10 +25,6 @@ macro_rules! raw_reg {
2525
fn mask<const WI: u8>() -> Self {
2626
$mask::<WI>()
2727
}
28-
#[inline(always)]
29-
fn one() -> Self {
30-
1
31-
}
3228
}
3329
const fn $mask<const WI: u8>() -> $U {
3430
<$U>::MAX >> ($size - WI)
@@ -74,10 +70,10 @@ pub trait Writable: RegisterSpec {
7470
type Safety;
7571

7672
/// Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`
77-
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux;
73+
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO;
7874

7975
/// Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`
80-
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux;
76+
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO;
8177
}
8278

8379
/// Reset value of the register.
@@ -86,7 +82,7 @@ pub trait Writable: RegisterSpec {
8682
/// register by using the `reset` method.
8783
pub trait Resettable: RegisterSpec {
8884
/// Reset value of the register.
89-
const RESET_VALUE: Self::Ux;
85+
const RESET_VALUE: Self::Ux = Self::Ux::ZERO;
9086

9187
/// Reset value of the register.
9288
#[inline(always)]
@@ -247,7 +243,10 @@ impl<REG: Writable> W<REG> {
247243
self
248244
}
249245
}
250-
impl<REG> W<REG> where REG: Writable<Safety = Safe> {
246+
impl<REG> W<REG>
247+
where
248+
REG: Writable<Safety = Safe>,
249+
{
251250
/// Writes raw bits to the register.
252251
#[inline(always)]
253252
pub fn set(&mut self, bits: REG::Ux) -> &mut Self {
@@ -335,7 +334,8 @@ pub struct RangeFrom<const MIN: u64>;
335334
pub struct RangeTo<const MAX: u64>;
336335

337336
/// Write field Proxy
338-
pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> = raw::FieldWriter<'a, REG, WI, FI, Safety>;
337+
pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
338+
raw::FieldWriter<'a, REG, WI, FI, Safety>;
339339

340340
impl<REG, const WI: u8, FI, Safety> FieldWriter<'_, REG, WI, FI, Safety>
341341
where
@@ -390,7 +390,8 @@ where
390390
}
391391
}
392392

393-
impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64> FieldWriter<'a, REG, WI, FI, Range<MIN, MAX>>
393+
impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64>
394+
FieldWriter<'a, REG, WI, FI, Range<MIN, MAX>>
394395
where
395396
REG: Writable + RegisterSpec,
396397
FI: FieldSpec,
@@ -478,7 +479,7 @@ macro_rules! bit_proxy {
478479
pub const fn width(&self) -> u8 {
479480
Self::WIDTH
480481
}
481-
482+
482483
/// Field offset
483484
#[inline(always)]
484485
pub const fn offset(&self) -> u8 {
@@ -488,8 +489,8 @@ macro_rules! bit_proxy {
488489
/// Writes bit to the field
489490
#[inline(always)]
490491
pub fn bit(self, value: bool) -> &'a mut W<REG> {
491-
self.w.bits &= !(REG::Ux::one() << self.o);
492-
self.w.bits |= (REG::Ux::from(value) & REG::Ux::one()) << self.o;
492+
self.w.bits &= !(REG::Ux::ONE << self.o);
493+
self.w.bits |= (REG::Ux::from(value) & REG::Ux::ONE) << self.o;
493494
self.w
494495
}
495496
/// Writes `variant` to the field
@@ -517,13 +518,13 @@ where
517518
/// Sets the field bit
518519
#[inline(always)]
519520
pub fn set_bit(self) -> &'a mut W<REG> {
520-
self.w.bits |= REG::Ux::one() << self.o;
521+
self.w.bits |= REG::Ux::ONE << self.o;
521522
self.w
522523
}
523524
/// Clears the field bit
524525
#[inline(always)]
525526
pub fn clear_bit(self) -> &'a mut W<REG> {
526-
self.w.bits &= !(REG::Ux::one() << self.o);
527+
self.w.bits &= !(REG::Ux::ONE << self.o);
527528
self.w
528529
}
529530
}
@@ -536,7 +537,7 @@ where
536537
/// Sets the field bit
537538
#[inline(always)]
538539
pub fn set_bit(self) -> &'a mut W<REG> {
539-
self.w.bits |= REG::Ux::one() << self.o;
540+
self.w.bits |= REG::Ux::ONE << self.o;
540541
self.w
541542
}
542543
}
@@ -549,7 +550,7 @@ where
549550
/// Clears the field bit
550551
#[inline(always)]
551552
pub fn clear_bit(self) -> &'a mut W<REG> {
552-
self.w.bits &= !(REG::Ux::one() << self.o);
553+
self.w.bits &= !(REG::Ux::ONE << self.o);
553554
self.w
554555
}
555556
}
@@ -562,7 +563,7 @@ where
562563
///Clears the field bit by passing one
563564
#[inline(always)]
564565
pub fn clear_bit_by_one(self) -> &'a mut W<REG> {
565-
self.w.bits |= REG::Ux::one() << self.o;
566+
self.w.bits |= REG::Ux::ONE << self.o;
566567
self.w
567568
}
568569
}
@@ -575,7 +576,7 @@ where
575576
///Sets the field bit by passing zero
576577
#[inline(always)]
577578
pub fn set_bit_by_zero(self) -> &'a mut W<REG> {
578-
self.w.bits &= !(REG::Ux::one() << self.o);
579+
self.w.bits &= !(REG::Ux::ONE << self.o);
579580
self.w
580581
}
581582
}
@@ -588,7 +589,7 @@ where
588589
///Toggle the field bit by passing one
589590
#[inline(always)]
590591
pub fn toggle_bit(self) -> &'a mut W<REG> {
591-
self.w.bits |= REG::Ux::one() << self.o;
592+
self.w.bits |= REG::Ux::ONE << self.o;
592593
self.w
593594
}
594595
}
@@ -601,7 +602,7 @@ where
601602
///Toggle the field bit by passing zero
602603
#[inline(always)]
603604
pub fn toggle_bit(self) -> &'a mut W<REG> {
604-
self.w.bits &= !(REG::Ux::one() << self.o);
605+
self.w.bits &= !(REG::Ux::ONE << self.o);
605606
self.w
606607
}
607608
}

‎src/generate/generic_atomic.rs

+4-4
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ mod atomic {
3939

4040
impl<REG: Readable + Writable> Reg<REG>
4141
where
42-
REG::Ux: AtomicOperations
42+
REG::Ux: AtomicOperations,
4343
{
4444
/// Set high every bit in the register that was set in the write proxy. Leave other bits
4545
/// untouched. The write is done in a single atomic instruction.
@@ -53,7 +53,7 @@ mod atomic {
5353
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
5454
{
5555
let bits = f(&mut W {
56-
bits: Default::default(),
56+
bits: REG::Ux::ZERO,
5757
_reg: marker::PhantomData,
5858
})
5959
.bits;
@@ -72,7 +72,7 @@ mod atomic {
7272
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
7373
{
7474
let bits = f(&mut W {
75-
bits: !REG::Ux::default(),
75+
bits: !REG::Ux::ZERO,
7676
_reg: marker::PhantomData,
7777
})
7878
.bits;
@@ -91,7 +91,7 @@ mod atomic {
9191
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
9292
{
9393
let bits = f(&mut W {
94-
bits: Default::default(),
94+
bits: REG::Ux::ZERO,
9595
_reg: marker::PhantomData,
9696
})
9797
.bits;

‎src/generate/generic_reg_vcell.rs

+2-2
Original file line numberDiff line numberDiff line change
@@ -148,7 +148,7 @@ impl<REG: Writable> Reg<REG> {
148148
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
149149
{
150150
let value = f(&mut W {
151-
bits: REG::Ux::default(),
151+
bits: REG::Ux::ZERO,
152152
_reg: marker::PhantomData,
153153
})
154154
.bits;
@@ -169,7 +169,7 @@ impl<REG: Writable> Reg<REG> {
169169
F: FnOnce(&mut W<REG>) -> T,
170170
{
171171
let mut writer = W {
172-
bits: REG::Ux::default(),
172+
bits: REG::Ux::ZERO,
173173
_reg: marker::PhantomData,
174174
};
175175

‎src/generate/register.rs

+14-7
Original file line numberDiff line numberDiff line change
@@ -413,24 +413,31 @@ pub fn render_register_mod(
413413

414414
let doc = format!("`write(|w| ..)` method takes [`{mod_ty}::W`](W) writer structure",);
415415

416-
let zero_to_modify_fields_bitmap = util::hex(zero_to_modify_fields_bitmap);
417-
let one_to_modify_fields_bitmap = util::hex(one_to_modify_fields_bitmap);
416+
let zero_to_modify_fields_bitmap = util::hex_nonzero(zero_to_modify_fields_bitmap)
417+
.map(|bm| quote!(const ZERO_TO_MODIFY_FIELDS_BITMAP: #rty = #bm;));
418+
let one_to_modify_fields_bitmap = util::hex_nonzero(one_to_modify_fields_bitmap)
419+
.map(|bm| quote!(const ONE_TO_MODIFY_FIELDS_BITMAP: #rty = #bm;));
418420

419421
mod_items.extend(quote! {
420422
#[doc = #doc]
421423
impl crate::Writable for #regspec_ty {
422424
type Safety = crate::#safe_ty;
423-
const ZERO_TO_MODIFY_FIELDS_BITMAP: #rty = #zero_to_modify_fields_bitmap;
424-
const ONE_TO_MODIFY_FIELDS_BITMAP: #rty = #one_to_modify_fields_bitmap;
425+
#zero_to_modify_fields_bitmap
426+
#one_to_modify_fields_bitmap
425427
}
426428
});
427429
}
428-
if let Some(rv) = properties.reset_value.map(util::hex) {
429-
let doc = format!("`reset()` method sets {} to value {rv}", register.name);
430+
if let Some(rv) = properties.reset_value.map(util::hex_nonzero) {
431+
let doc = if let Some(rv) = &rv {
432+
format!("`reset()` method sets {} to value {rv}", register.name)
433+
} else {
434+
format!("`reset()` method sets {} to value 0", register.name)
435+
};
436+
let rv = rv.map(|rv| quote!(const RESET_VALUE: #rty = #rv;));
430437
mod_items.extend(quote! {
431438
#[doc = #doc]
432439
impl crate::Resettable for #regspec_ty {
433-
const RESET_VALUE: #rty = #rv;
440+
#rv
434441
}
435442
});
436443
}

‎src/lib.rs

+5
Original file line numberDiff line numberDiff line change
@@ -62,6 +62,7 @@
6262
//! - [`cortex-m`](https://crates.io/crates/cortex-m) >=v0.7.6
6363
//! - [`cortex-m-rt`](https://crates.io/crates/cortex-m-rt) >=v0.6.13
6464
//! - [`vcell`](https://crates.io/crates/vcell) >=v0.1.2
65+
//! - [`num-traits`](https://crates.io/crates/const-default) >=v0.2.18
6566
//!
6667
//! Furthermore, the "device" feature of `cortex-m-rt` must be enabled when the `rt` feature
6768
//! is enabled. The `Cargo.toml` of the device crate will look like this:
@@ -126,6 +127,7 @@
126127
//! - [`msp430`](https://crates.io/crates/msp430) v0.4.x
127128
//! - [`msp430-rt`](https://crates.io/crates/msp430-rt) v0.4.x
128129
//! - [`vcell`](https://crates.io/crates/vcell) v0.1.x
130+
//! - [`num-traits`](https://crates.io/crates/const-default) v0.2.x
129131
//!
130132
//! The "device" feature of `msp430-rt` must be enabled when the `rt` feature is
131133
//! enabled. The `Cargo.toml` of the device crate will look like this:
@@ -136,6 +138,7 @@
136138
//! msp430 = "0.4.0"
137139
//! msp430-rt = { version = "0.4.0", optional = true }
138140
//! vcell = "0.1.0"
141+
//! num-traits = { version = "0.2.19", default-features = false }
139142
//!
140143
//! [features]
141144
//! rt = ["msp430-rt/device"]
@@ -153,6 +156,7 @@
153156
//! - [`riscv-peripheral`](https://crates.io/crates/riscv-peripheral) v0.2.x (if target is RISC-V and has standard peripherals)
154157
//! - [`riscv-rt`](https://crates.io/crates/riscv-rt) v0.13.x (if target is RISC-V)
155158
//! - [`vcell`](https://crates.io/crates/vcell) v0.1.x
159+
//! - [`num-traits`](https://crates.io/crates/const-default) v0.2.x
156160
//!
157161
//! The `*-rt` dependencies must be optional only enabled when the `rt` feature is enabled.
158162
//! If target is RISC-V and supports vectored mode, you must include a feature `v-trap` to activate `riscv-rt/v-trap`.
@@ -165,6 +169,7 @@
165169
//! riscv-peripheral = "0.2.0"
166170
//! riscv-rt = { version = "0.13.0", optional = true }
167171
//! vcell = "0.1.0"
172+
//! num-traits = { version = "0.2.19", default-features = false }
168173
//!
169174
//! [features]
170175
//! rt = ["riscv-rt"]

‎src/util.rs

+5
Original file line numberDiff line numberDiff line change
@@ -255,6 +255,11 @@ pub fn hex(n: u64) -> LitInt {
255255
)
256256
}
257257

258+
/// Turns non-zero `n` into an unsuffixed separated hex token
259+
pub fn hex_nonzero(n: u64) -> Option<LitInt> {
260+
(n != 0).then(|| hex(n))
261+
}
262+
258263
/// Turns `n` into an unsuffixed token
259264
pub fn unsuffixed(n: impl Into<u64>) -> LitInt {
260265
LitInt::new(&n.into().to_string(), Span::call_site())

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