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[InstCombine] Fold select (icmp sgt x, -1), lshr (X, Y), ashr (X, Y) to ashr (X, Y))
Summary: (select (icmp sgt x, -1), lshr (X, Y), ashr (X, Y)) -> ashr (X, Y)) (select (icmp slt x, 1), ashr (X, Y), lshr (X, Y)) -> ashr (X, Y)) Fixes PR41173 Alive proof by @lebedev.ri (thanks) Name: PR41173 %cmp = icmp slt i32 %x, 1 %shr = lshr i32 %x, %y %shr1 = ashr i32 %x, %y %retval.0 = select i1 %cmp, i32 %shr1, i32 %shr => %retval.0 = ashr i32 %x, %y Optimization: PR41173 Done: 1 Optimization is correct! Reviewers: lebedev.ri, spatel Reviewed By: lebedev.ri Subscribers: nikic, craig.topper, llvm-commits, lebedev.ri Tags: #llvm Differential Revision: https://reviews.llvm.org/D64285 llvm-svn: 365893
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‎llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

+41
Original file line numberDiff line numberDiff line change
@@ -531,6 +531,44 @@ static Instruction *foldSelectICmpAndAnd(Type *SelType, const ICmpInst *Cmp,
531531
return new ZExtInst(ICmpNeZero, SelType);
532532
}
533533

534+
/// We want to turn:
535+
/// (select (icmp sgt x, C), lshr (X, Y), ashr (X, Y)); iff C s>= -1
536+
/// (select (icmp slt x, C), ashr (X, Y), lshr (X, Y)); iff C s>= 0
537+
/// into:
538+
/// ashr (X, Y)
539+
static Value *foldSelectICmpLshrAshr(const ICmpInst *IC, Value *TrueVal,
540+
Value *FalseVal,
541+
InstCombiner::BuilderTy &Builder) {
542+
ICmpInst::Predicate Pred = IC->getPredicate();
543+
Value *CmpLHS = IC->getOperand(0);
544+
Value *CmpRHS = IC->getOperand(1);
545+
546+
Value *X, *Y;
547+
unsigned Bitwidth = CmpRHS->getType()->getScalarSizeInBits();
548+
if ((Pred != ICmpInst::ICMP_SGT ||
549+
!match(CmpRHS,
550+
m_SpecificInt_ICMP(ICmpInst::ICMP_SGE, APInt(Bitwidth, -1)))) &&
551+
(Pred != ICmpInst::ICMP_SLT ||
552+
!match(CmpRHS,
553+
m_SpecificInt_ICMP(ICmpInst::ICMP_SGE, APInt(Bitwidth, 0)))))
554+
return nullptr;
555+
556+
// Canonicalize so that ashr is in FalseVal.
557+
if (Pred == ICmpInst::ICMP_SLT)
558+
std::swap(TrueVal, FalseVal);
559+
560+
if (match(TrueVal, m_LShr(m_Value(X), m_Value(Y))) &&
561+
match(FalseVal, m_AShr(m_Specific(X), m_Specific(Y))) &&
562+
match(CmpLHS, m_Specific(X))) {
563+
const auto *Ashr = cast<Instruction>(FalseVal);
564+
// if lshr is not exact and ashr is, this new ashr must not be exact.
565+
bool IsExact = Ashr->isExact() && cast<Instruction>(TrueVal)->isExact();
566+
return Builder.CreateAShr(X, Y, IC->getName(), IsExact);
567+
}
568+
569+
return nullptr;
570+
}
571+
534572
/// We want to turn:
535573
/// (select (icmp eq (and X, C1), 0), Y, (or Y, C2))
536574
/// into:
@@ -1112,6 +1150,9 @@ Instruction *InstCombiner::foldSelectInstWithICmp(SelectInst &SI,
11121150
if (Value *V = foldSelectICmpAndOr(ICI, TrueVal, FalseVal, Builder))
11131151
return replaceInstUsesWith(SI, V);
11141152

1153+
if (Value *V = foldSelectICmpLshrAshr(ICI, TrueVal, FalseVal, Builder))
1154+
return replaceInstUsesWith(SI, V);
1155+
11151156
if (Value *V = foldSelectCttzCtlz(ICI, TrueVal, FalseVal, Builder))
11161157
return replaceInstUsesWith(SI, V);
11171158

‎llvm/test/Transforms/InstCombine/ashr-lshr.ll

+42-105
Original file line numberDiff line numberDiff line change
@@ -3,11 +3,8 @@
33

44
define i32 @ashr_lshr_exact_ashr_only(i32 %x, i32 %y) {
55
; CHECK-LABEL: @ashr_lshr_exact_ashr_only(
6-
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
7-
; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
8-
; CHECK-NEXT: [[R:%.*]] = ashr exact i32 [[X]], [[Y]]
9-
; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
10-
; CHECK-NEXT: ret i32 [[RET]]
6+
; CHECK-NEXT: [[CMP1:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
7+
; CHECK-NEXT: ret i32 [[CMP1]]
118
;
129
%cmp = icmp sgt i32 %x, -1
1310
%l = lshr i32 %x, %y
@@ -18,11 +15,8 @@ define i32 @ashr_lshr_exact_ashr_only(i32 %x, i32 %y) {
1815

1916
define i32 @ashr_lshr_no_exact(i32 %x, i32 %y) {
2017
; CHECK-LABEL: @ashr_lshr_no_exact(
21-
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
22-
; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
23-
; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
24-
; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
25-
; CHECK-NEXT: ret i32 [[RET]]
18+
; CHECK-NEXT: [[CMP1:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
19+
; CHECK-NEXT: ret i32 [[CMP1]]
2620
;
2721
%cmp = icmp sgt i32 %x, -1
2822
%l = lshr i32 %x, %y
@@ -33,11 +27,8 @@ define i32 @ashr_lshr_no_exact(i32 %x, i32 %y) {
3327

3428
define i32 @ashr_lshr_exact_both(i32 %x, i32 %y) {
3529
; CHECK-LABEL: @ashr_lshr_exact_both(
36-
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
37-
; CHECK-NEXT: [[L:%.*]] = lshr exact i32 [[X]], [[Y:%.*]]
38-
; CHECK-NEXT: [[R:%.*]] = ashr exact i32 [[X]], [[Y]]
39-
; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
40-
; CHECK-NEXT: ret i32 [[RET]]
30+
; CHECK-NEXT: [[CMP1:%.*]] = ashr exact i32 [[X:%.*]], [[Y:%.*]]
31+
; CHECK-NEXT: ret i32 [[CMP1]]
4132
;
4233
%cmp = icmp sgt i32 %x, -1
4334
%l = lshr exact i32 %x, %y
@@ -48,11 +39,8 @@ define i32 @ashr_lshr_exact_both(i32 %x, i32 %y) {
4839

4940
define i32 @ashr_lshr_exact_lshr_only(i32 %x, i32 %y) {
5041
; CHECK-LABEL: @ashr_lshr_exact_lshr_only(
51-
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
52-
; CHECK-NEXT: [[L:%.*]] = lshr exact i32 [[X]], [[Y:%.*]]
53-
; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
54-
; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
55-
; CHECK-NEXT: ret i32 [[RET]]
42+
; CHECK-NEXT: [[CMP1:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
43+
; CHECK-NEXT: ret i32 [[CMP1]]
5644
;
5745
%cmp = icmp sgt i32 %x, -1
5846
%l = lshr exact i32 %x, %y
@@ -63,11 +51,8 @@ define i32 @ashr_lshr_exact_lshr_only(i32 %x, i32 %y) {
6351

6452
define i32 @ashr_lshr2(i32 %x, i32 %y) {
6553
; CHECK-LABEL: @ashr_lshr2(
66-
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], 5
67-
; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
68-
; CHECK-NEXT: [[R:%.*]] = ashr exact i32 [[X]], [[Y]]
69-
; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
70-
; CHECK-NEXT: ret i32 [[RET]]
54+
; CHECK-NEXT: [[CMP1:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
55+
; CHECK-NEXT: ret i32 [[CMP1]]
7156
;
7257
%cmp = icmp sgt i32 %x, 5
7358
%l = lshr i32 %x, %y
@@ -78,11 +63,8 @@ define i32 @ashr_lshr2(i32 %x, i32 %y) {
7863

7964
define <2 x i32> @ashr_lshr_splat_vec(<2 x i32> %x, <2 x i32> %y) {
8065
; CHECK-LABEL: @ashr_lshr_splat_vec(
81-
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
82-
; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
83-
; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
84-
; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
85-
; CHECK-NEXT: ret <2 x i32> [[RET]]
66+
; CHECK-NEXT: [[CMP1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
67+
; CHECK-NEXT: ret <2 x i32> [[CMP1]]
8668
;
8769
%cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
8870
%l = lshr <2 x i32> %x, %y
@@ -93,11 +75,8 @@ define <2 x i32> @ashr_lshr_splat_vec(<2 x i32> %x, <2 x i32> %y) {
9375

9476
define <2 x i32> @ashr_lshr_splat_vec2(<2 x i32> %x, <2 x i32> %y) {
9577
; CHECK-LABEL: @ashr_lshr_splat_vec2(
96-
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
97-
; CHECK-NEXT: [[L:%.*]] = lshr exact <2 x i32> [[X]], [[Y:%.*]]
98-
; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
99-
; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
100-
; CHECK-NEXT: ret <2 x i32> [[RET]]
78+
; CHECK-NEXT: [[CMP1:%.*]] = ashr exact <2 x i32> [[X:%.*]], [[Y:%.*]]
79+
; CHECK-NEXT: ret <2 x i32> [[CMP1]]
10180
;
10281
%cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
10382
%l = lshr exact <2 x i32> %x, %y
@@ -108,11 +87,8 @@ define <2 x i32> @ashr_lshr_splat_vec2(<2 x i32> %x, <2 x i32> %y) {
10887

10988
define <2 x i32> @ashr_lshr_splat_vec3(<2 x i32> %x, <2 x i32> %y) {
11089
; CHECK-LABEL: @ashr_lshr_splat_vec3(
111-
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
112-
; CHECK-NEXT: [[L:%.*]] = lshr exact <2 x i32> [[X]], [[Y:%.*]]
113-
; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
114-
; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
115-
; CHECK-NEXT: ret <2 x i32> [[RET]]
90+
; CHECK-NEXT: [[CMP1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
91+
; CHECK-NEXT: ret <2 x i32> [[CMP1]]
11692
;
11793
%cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
11894
%l = lshr exact <2 x i32> %x, %y
@@ -123,11 +99,8 @@ define <2 x i32> @ashr_lshr_splat_vec3(<2 x i32> %x, <2 x i32> %y) {
12399

124100
define <2 x i32> @ashr_lshr_splat_vec4(<2 x i32> %x, <2 x i32> %y) {
125101
; CHECK-LABEL: @ashr_lshr_splat_vec4(
126-
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
127-
; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
128-
; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
129-
; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
130-
; CHECK-NEXT: ret <2 x i32> [[RET]]
102+
; CHECK-NEXT: [[CMP1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
103+
; CHECK-NEXT: ret <2 x i32> [[CMP1]]
131104
;
132105
%cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
133106
%l = lshr <2 x i32> %x, %y
@@ -138,11 +111,8 @@ define <2 x i32> @ashr_lshr_splat_vec4(<2 x i32> %x, <2 x i32> %y) {
138111

139112
define <2 x i32> @ashr_lshr_nonsplat_vec(<2 x i32> %x, <2 x i32> %y) {
140113
; CHECK-LABEL: @ashr_lshr_nonsplat_vec(
141-
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 1>
142-
; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
143-
; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
144-
; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
145-
; CHECK-NEXT: ret <2 x i32> [[RET]]
114+
; CHECK-NEXT: [[CMP1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
115+
; CHECK-NEXT: ret <2 x i32> [[CMP1]]
146116
;
147117
%cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 1>
148118
%l = lshr <2 x i32> %x, %y
@@ -153,11 +123,8 @@ define <2 x i32> @ashr_lshr_nonsplat_vec(<2 x i32> %x, <2 x i32> %y) {
153123

154124
define <2 x i32> @ashr_lshr_nonsplat_vec2(<2 x i32> %x, <2 x i32> %y) {
155125
; CHECK-LABEL: @ashr_lshr_nonsplat_vec2(
156-
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 2, i32 4>
157-
; CHECK-NEXT: [[L:%.*]] = lshr exact <2 x i32> [[X]], [[Y:%.*]]
158-
; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
159-
; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
160-
; CHECK-NEXT: ret <2 x i32> [[RET]]
126+
; CHECK-NEXT: [[CMP1:%.*]] = ashr exact <2 x i32> [[X:%.*]], [[Y:%.*]]
127+
; CHECK-NEXT: ret <2 x i32> [[CMP1]]
161128
;
162129
%cmp = icmp sgt <2 x i32> %x, <i32 2, i32 4>
163130
%l = lshr exact <2 x i32> %x, %y
@@ -168,11 +135,8 @@ define <2 x i32> @ashr_lshr_nonsplat_vec2(<2 x i32> %x, <2 x i32> %y) {
168135

169136
define <2 x i32> @ashr_lshr_nonsplat_vec3(<2 x i32> %x, <2 x i32> %y) {
170137
; CHECK-LABEL: @ashr_lshr_nonsplat_vec3(
171-
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 5, i32 6>
172-
; CHECK-NEXT: [[L:%.*]] = lshr exact <2 x i32> [[X]], [[Y:%.*]]
173-
; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
174-
; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
175-
; CHECK-NEXT: ret <2 x i32> [[RET]]
138+
; CHECK-NEXT: [[CMP1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
139+
; CHECK-NEXT: ret <2 x i32> [[CMP1]]
176140
;
177141
%cmp = icmp sgt <2 x i32> %x, <i32 5, i32 6>
178142
%l = lshr exact <2 x i32> %x, %y
@@ -183,11 +147,8 @@ define <2 x i32> @ashr_lshr_nonsplat_vec3(<2 x i32> %x, <2 x i32> %y) {
183147

184148
define <2 x i32> @ashr_lshr_nonsplat_vec4(<2 x i32> %x, <2 x i32> %y) {
185149
; CHECK-LABEL: @ashr_lshr_nonsplat_vec4(
186-
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 8, i32 7>
187-
; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
188-
; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
189-
; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
190-
; CHECK-NEXT: ret <2 x i32> [[RET]]
150+
; CHECK-NEXT: [[CMP1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
151+
; CHECK-NEXT: ret <2 x i32> [[CMP1]]
191152
;
192153
%cmp = icmp sgt <2 x i32> %x, <i32 8, i32 7>
193154
%l = lshr <2 x i32> %x, %y
@@ -198,11 +159,8 @@ define <2 x i32> @ashr_lshr_nonsplat_vec4(<2 x i32> %x, <2 x i32> %y) {
198159

199160
define i32 @ashr_lshr_cst(i32 %x, i32 %y) {
200161
; CHECK-LABEL: @ashr_lshr_cst(
201-
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 1
202-
; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], 8
203-
; CHECK-NEXT: [[R:%.*]] = ashr exact i32 [[X]], 8
204-
; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[R]], i32 [[L]]
205-
; CHECK-NEXT: ret i32 [[RET]]
162+
; CHECK-NEXT: [[CMP1:%.*]] = ashr i32 [[X:%.*]], 8
163+
; CHECK-NEXT: ret i32 [[CMP1]]
206164
;
207165
%cmp = icmp slt i32 %x, 1
208166
%l = lshr i32 %x, 8
@@ -213,11 +171,8 @@ define i32 @ashr_lshr_cst(i32 %x, i32 %y) {
213171

214172
define i32 @ashr_lshr_cst2(i32 %x, i32 %y) {
215173
; CHECK-LABEL: @ashr_lshr_cst2(
216-
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
217-
; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], 8
218-
; CHECK-NEXT: [[R:%.*]] = ashr exact i32 [[X]], 8
219-
; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
220-
; CHECK-NEXT: ret i32 [[RET]]
174+
; CHECK-NEXT: [[CMP1:%.*]] = ashr i32 [[X:%.*]], 8
175+
; CHECK-NEXT: ret i32 [[CMP1]]
221176
;
222177
%cmp = icmp sgt i32 %x, -1
223178
%l = lshr i32 %x, 8
@@ -228,11 +183,8 @@ define i32 @ashr_lshr_cst2(i32 %x, i32 %y) {
228183

229184
define i32 @ashr_lshr_inv(i32 %x, i32 %y) {
230185
; CHECK-LABEL: @ashr_lshr_inv(
231-
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 1
232-
; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
233-
; CHECK-NEXT: [[R:%.*]] = ashr exact i32 [[X]], [[Y]]
234-
; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[R]], i32 [[L]]
235-
; CHECK-NEXT: ret i32 [[RET]]
186+
; CHECK-NEXT: [[CMP1:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
187+
; CHECK-NEXT: ret i32 [[CMP1]]
236188
;
237189
%cmp = icmp slt i32 %x, 1
238190
%l = lshr i32 %x, %y
@@ -243,11 +195,8 @@ define i32 @ashr_lshr_inv(i32 %x, i32 %y) {
243195

244196
define i32 @ashr_lshr_inv2(i32 %x, i32 %y) {
245197
; CHECK-LABEL: @ashr_lshr_inv2(
246-
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 7
247-
; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
248-
; CHECK-NEXT: [[R:%.*]] = ashr exact i32 [[X]], [[Y]]
249-
; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[R]], i32 [[L]]
250-
; CHECK-NEXT: ret i32 [[RET]]
198+
; CHECK-NEXT: [[CMP1:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
199+
; CHECK-NEXT: ret i32 [[CMP1]]
251200
;
252201
%cmp = icmp slt i32 %x, 7
253202
%l = lshr i32 %x, %y
@@ -258,11 +207,8 @@ define i32 @ashr_lshr_inv2(i32 %x, i32 %y) {
258207

259208
define <2 x i32> @ashr_lshr_inv_splat_vec(<2 x i32> %x, <2 x i32> %y) {
260209
; CHECK-LABEL: @ashr_lshr_inv_splat_vec(
261-
; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]], <i32 1, i32 1>
262-
; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
263-
; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
264-
; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[R]], <2 x i32> [[L]]
265-
; CHECK-NEXT: ret <2 x i32> [[RET]]
210+
; CHECK-NEXT: [[CMP1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
211+
; CHECK-NEXT: ret <2 x i32> [[CMP1]]
266212
;
267213
%cmp = icmp slt <2 x i32> %x, <i32 1, i32 1>
268214
%l = lshr <2 x i32> %x, %y
@@ -273,11 +219,8 @@ define <2 x i32> @ashr_lshr_inv_splat_vec(<2 x i32> %x, <2 x i32> %y) {
273219

274220
define <2 x i32> @ashr_lshr_inv_nonsplat_vec(<2 x i32> %x, <2 x i32> %y) {
275221
; CHECK-LABEL: @ashr_lshr_inv_nonsplat_vec(
276-
; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]], <i32 4, i32 5>
277-
; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
278-
; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
279-
; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[R]], <2 x i32> [[L]]
280-
; CHECK-NEXT: ret <2 x i32> [[RET]]
222+
; CHECK-NEXT: [[CMP1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
223+
; CHECK-NEXT: ret <2 x i32> [[CMP1]]
281224
;
282225
%cmp = icmp slt <2 x i32> %x, <i32 4, i32 5>
283226
%l = lshr <2 x i32> %x, %y
@@ -288,11 +231,8 @@ define <2 x i32> @ashr_lshr_inv_nonsplat_vec(<2 x i32> %x, <2 x i32> %y) {
288231

289232
define <2 x i32> @ashr_lshr_vec_undef(<2 x i32> %x, <2 x i32> %y) {
290233
; CHECK-LABEL: @ashr_lshr_vec_undef(
291-
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 undef, i32 -1>
292-
; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
293-
; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
294-
; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
295-
; CHECK-NEXT: ret <2 x i32> [[RET]]
234+
; CHECK-NEXT: [[CMP1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
235+
; CHECK-NEXT: ret <2 x i32> [[CMP1]]
296236
;
297237
%cmp = icmp sgt <2 x i32> %x, <i32 undef, i32 -1>
298238
%l = lshr <2 x i32> %x, %y
@@ -303,11 +243,8 @@ define <2 x i32> @ashr_lshr_vec_undef(<2 x i32> %x, <2 x i32> %y) {
303243

304244
define <2 x i32> @ashr_lshr_vec_undef2(<2 x i32> %x, <2 x i32> %y) {
305245
; CHECK-LABEL: @ashr_lshr_vec_undef2(
306-
; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]], <i32 1, i32 undef>
307-
; CHECK-NEXT: [[L:%.*]] = lshr exact <2 x i32> [[X]], [[Y:%.*]]
308-
; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
309-
; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[R]], <2 x i32> [[L]]
310-
; CHECK-NEXT: ret <2 x i32> [[RET]]
246+
; CHECK-NEXT: [[CMP1:%.*]] = ashr exact <2 x i32> [[X:%.*]], [[Y:%.*]]
247+
; CHECK-NEXT: ret <2 x i32> [[CMP1]]
311248
;
312249
%cmp = icmp slt <2 x i32> %x, <i32 1, i32 undef>
313250
%l = lshr exact <2 x i32> %x, %y

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