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Auto merge of #43492 - lu-zero:master, r=alexcrichton
More Altivec Intrinsics
2 parents 42a09c0 + c471020 commit 6dd8744

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6 files changed

+186
-17
lines changed

6 files changed

+186
-17
lines changed

‎src/etc/platform-intrinsics/powerpc.json

+58-2
Original file line numberDiff line numberDiff line change
@@ -3,8 +3,15 @@
33
"intrinsic_prefix": "_vec_",
44
"llvm_prefix": "llvm.ppc.altivec.",
55
"number_info": {
6-
"unsigned": {},
7-
"signed": {}
6+
"unsigned": {
7+
"kind" : "u",
8+
"data_type_short": { "8": "b", "16": "h", "32": "w", "64": "d" }
9+
},
10+
"signed": {
11+
"kind" : "s",
12+
"data_type_short": { "8": "b", "16": "h", "32": "w", "64": "d" }
13+
},
14+
"float": {}
815
},
916
"width_info": {
1017
"128": { "width": "" }
@@ -16,6 +23,55 @@
1623
"llvm": "vperm",
1724
"ret": "s32",
1825
"args": ["0", "0", "s8"]
26+
},
27+
{
28+
"intrinsic": "mradds",
29+
"width": [128],
30+
"llvm": "vmhraddshs",
31+
"ret": "s16",
32+
"args": ["0", "0", "0"]
33+
},
34+
{
35+
"intrinsic": "cmpb",
36+
"width": [128],
37+
"llvm": "vcmpbfp",
38+
"ret": "s32",
39+
"args": ["f32", "f32"]
40+
},
41+
{
42+
"intrinsic": "cmpeq{0.data_type_short}",
43+
"width": [128],
44+
"llvm": "vcmpequ{0.data_type_short}",
45+
"ret": "s(8-32)",
46+
"args": ["0", "0"]
47+
},
48+
{
49+
"intrinsic": "cmpgt{1.kind}{1.data_type_short}",
50+
"width": [128],
51+
"llvm": "vcmpgt{1.kind}{1.data_type_short}",
52+
"ret": "s(8-32)",
53+
"args": ["0u", "1"]
54+
},
55+
{
56+
"intrinsic": "cmpgt{1.kind}{1.data_type_short}",
57+
"width": [128],
58+
"llvm": "vcmpgt{1.kind}{1.data_type_short}",
59+
"ret": "s(8-32)",
60+
"args": ["0", "1"]
61+
},
62+
{
63+
"intrinsic": "max{0.kind}{0.data_type_short}",
64+
"width": [128],
65+
"llvm": "vmax{0.kind}{0.data_type_short}",
66+
"ret": "i(8-32)",
67+
"args": ["0", "0"]
68+
},
69+
{
70+
"intrinsic": "min{0.kind}{0.data_type_short}",
71+
"width": [128],
72+
"llvm": "vmin{0.kind}{0.data_type_short}",
73+
"ret": "i(8-32)",
74+
"args": ["0", "0"]
1975
}
2076
]
2177
}

‎src/librustc_platform_intrinsics/powerpc.rs

+115
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,121 @@ pub fn find(name: &str) -> Option<Intrinsic> {
2727
output: &::I32x4,
2828
definition: Named("llvm.ppc.altivec.vperm")
2929
},
30+
"_vec_mradds" => Intrinsic {
31+
inputs: { static INPUTS: [&'static Type; 3] = [&::I16x8, &::I16x8, &::I16x8]; &INPUTS },
32+
output: &::I16x8,
33+
definition: Named("llvm.ppc.altivec.vmhraddshs")
34+
},
35+
"_vec_cmpb" => Intrinsic {
36+
inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
37+
output: &::I32x4,
38+
definition: Named("llvm.ppc.altivec.vcmpbfp")
39+
},
40+
"_vec_cmpeqb" => Intrinsic {
41+
inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
42+
output: &::I8x16,
43+
definition: Named("llvm.ppc.altivec.vcmpequb")
44+
},
45+
"_vec_cmpeqh" => Intrinsic {
46+
inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
47+
output: &::I16x8,
48+
definition: Named("llvm.ppc.altivec.vcmpequh")
49+
},
50+
"_vec_cmpeqw" => Intrinsic {
51+
inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
52+
output: &::I32x4,
53+
definition: Named("llvm.ppc.altivec.vcmpequw")
54+
},
55+
"_vec_cmpgtub" => Intrinsic {
56+
inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
57+
output: &::I8x16,
58+
definition: Named("llvm.ppc.altivec.vcmpgtub")
59+
},
60+
"_vec_cmpgtuh" => Intrinsic {
61+
inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
62+
output: &::I16x8,
63+
definition: Named("llvm.ppc.altivec.vcmpgtuh")
64+
},
65+
"_vec_cmpgtuw" => Intrinsic {
66+
inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
67+
output: &::I32x4,
68+
definition: Named("llvm.ppc.altivec.vcmpgtuw")
69+
},
70+
"_vec_cmpgtsb" => Intrinsic {
71+
inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
72+
output: &::I8x16,
73+
definition: Named("llvm.ppc.altivec.vcmpgtsb")
74+
},
75+
"_vec_cmpgtsh" => Intrinsic {
76+
inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
77+
output: &::I16x8,
78+
definition: Named("llvm.ppc.altivec.vcmpgtsh")
79+
},
80+
"_vec_cmpgtsw" => Intrinsic {
81+
inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
82+
output: &::I32x4,
83+
definition: Named("llvm.ppc.altivec.vcmpgtsw")
84+
},
85+
"_vec_maxsb" => Intrinsic {
86+
inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
87+
output: &::I8x16,
88+
definition: Named("llvm.ppc.altivec.vmaxsb")
89+
},
90+
"_vec_maxub" => Intrinsic {
91+
inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
92+
output: &::U8x16,
93+
definition: Named("llvm.ppc.altivec.vmaxub")
94+
},
95+
"_vec_maxsh" => Intrinsic {
96+
inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
97+
output: &::I16x8,
98+
definition: Named("llvm.ppc.altivec.vmaxsh")
99+
},
100+
"_vec_maxuh" => Intrinsic {
101+
inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
102+
output: &::U16x8,
103+
definition: Named("llvm.ppc.altivec.vmaxuh")
104+
},
105+
"_vec_maxsw" => Intrinsic {
106+
inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
107+
output: &::I32x4,
108+
definition: Named("llvm.ppc.altivec.vmaxsw")
109+
},
110+
"_vec_maxuw" => Intrinsic {
111+
inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
112+
output: &::U32x4,
113+
definition: Named("llvm.ppc.altivec.vmaxuw")
114+
},
115+
"_vec_minsb" => Intrinsic {
116+
inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
117+
output: &::I8x16,
118+
definition: Named("llvm.ppc.altivec.vminsb")
119+
},
120+
"_vec_minub" => Intrinsic {
121+
inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
122+
output: &::U8x16,
123+
definition: Named("llvm.ppc.altivec.vminub")
124+
},
125+
"_vec_minsh" => Intrinsic {
126+
inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
127+
output: &::I16x8,
128+
definition: Named("llvm.ppc.altivec.vminsh")
129+
},
130+
"_vec_minuh" => Intrinsic {
131+
inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
132+
output: &::U16x8,
133+
definition: Named("llvm.ppc.altivec.vminuh")
134+
},
135+
"_vec_minsw" => Intrinsic {
136+
inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
137+
output: &::I32x4,
138+
definition: Named("llvm.ppc.altivec.vminsw")
139+
},
140+
"_vec_minuw" => Intrinsic {
141+
inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
142+
output: &::U32x4,
143+
definition: Named("llvm.ppc.altivec.vminuw")
144+
},
30145
_ => return None,
31146
})
32147
}

‎src/librustc_trans/llvm_util.rs

+4-1
Original file line numberDiff line numberDiff line change
@@ -80,7 +80,10 @@ const X86_WHITELIST: &'static [&'static str] = &["avx\0", "avx2\0", "bmi\0", "bm
8080

8181
const HEXAGON_WHITELIST: &'static [&'static str] = &["hvx\0", "hvx-double\0"];
8282

83-
const POWERPC_WHITELIST: &'static [&'static str] = &["altivec\0", "vsx\0"];
83+
const POWERPC_WHITELIST: &'static [&'static str] = &["altivec\0",
84+
"power8-altivec\0", "power9-altivec\0",
85+
"power8-vector\0", "power9-vector\0",
86+
"vsx\0"];
8487

8588
pub fn target_features(sess: &Session) -> Vec<Symbol> {
8689
let target_machine = create_target_machine(sess);

‎src/rustllvm/PassWrapper.cpp

+7-13
Original file line numberDiff line numberDiff line change
@@ -181,20 +181,14 @@ extern "C" bool LLVMRustHasFeature(LLVMTargetMachineRef TM,
181181
TargetMachine *Target = unwrap(TM);
182182
const MCSubtargetInfo *MCInfo = Target->getMCSubtargetInfo();
183183
const FeatureBitset &Bits = MCInfo->getFeatureBits();
184-
const llvm::SubtargetFeatureKV *FeatureEntry;
185-
186-
#define SUBTARGET(x) \
187-
if (MCInfo->isCPUStringValid(x##SubTypeKV[0].Key)) { \
188-
FeatureEntry = x##FeatureKV; \
189-
} else
190-
191-
GEN_SUBTARGETS { return false; }
192-
#undef SUBTARGET
193-
194-
while (strcmp(Feature, FeatureEntry->Key) != 0)
195-
FeatureEntry++;
184+
#if LLVM_VERSION_GE(4, 0)
185+
const ArrayRef<SubtargetFeatureKV> FeatTable = MCInfo->getFeatureTable();
196186

197-
return (Bits & FeatureEntry->Value) == FeatureEntry->Value;
187+
for (auto &FeatureEntry : FeatTable)
188+
if (!strcmp(FeatureEntry.Key, Feature))
189+
return (Bits & FeatureEntry.Value) == FeatureEntry.Value;
190+
#endif
191+
return false;
198192
}
199193

200194
enum class LLVMRustCodeModel {

‎src/test/run-make/print-cfg/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ all: default
55
$(RUSTC) --target x86_64-pc-windows-gnu --print cfg | grep x86_64
66
$(RUSTC) --target i686-pc-windows-msvc --print cfg | grep msvc
77
$(RUSTC) --target i686-apple-darwin --print cfg | grep macos
8-
$(RUSTC) --target i686-unknown-linux-gnu --print cfg | grep sse2
8+
$(RUSTC) --target i686-unknown-linux-gnu --print cfg | grep gnu
99

1010
ifdef IS_WINDOWS
1111
default:

‎src/test/run-pass/sse2.rs

+1
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@
77
// <LICENSE-MIT or http://opensource.org/licenses/MIT>, at your
88
// option. This file may not be copied, modified, or distributed
99
// except according to those terms.
10+
// min-llvm-version 4.0
1011

1112
#![feature(cfg_target_feature)]
1213

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