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Auto merge of #147996 - pmur:murp/stabilize-ppc-inlineasm, r=Amanieu
Stabilize ppc inline assembly This stabilizes inline assembly for PowerPC and PowerPC64. Corresponding reference PR: rust-lang/reference#2056 --- From the requirements of stabilization mentioned in #93335 > Each architecture needs to be reviewed before stabilization: > * It must have clobber_abi. Done in #146949. > * It must be possible to clobber every register that is normally clobbered by a function call. Done in #131341 Similarly, `preserves_flags` is also implemented by this PR. Likewise, there is a non-code change to `preserve_flags` expectations that floating point and vector status and sticky bits are preserved. The reference manual update has more details. > * Generally review that the exposed register classes make sense. The followings can be used as input/output: * reg (`r0`, `r[3-12]`, `r[14-r28]`): Any usable general-purpose register * reg_nonzero (`r[3-12]`, `r[14-r28]`): General-purpose registers, but excludes `r0`. This is needed for instructions which define `r0` to be the value 0, such as register + immediate memory operations. * reg/reg_nonzero `r29` on PowerPC64 targets. * freg (`f[0-31]`): 64 bit floating pointer registers The following are clobber-only: * `ctr`, `lr`, `xer`: commonly clobbered special-purpose registers used in inline asm * `cr` (`cr[0-7]`, `cr`): the condition register fields, or the entire condition register. * `vreg` (`v[0-31]`): altivec/vmx register * `vsreg` (`vs[0-63]`): vector-scalar register * `spe_acc`: SPE accumulator, only available for PowerPC SPE targets. The vreg and vsreg registers technically accept `#[repr(simd)]` types, but require the experimental `altivec` or `vsx` target features to be enabled. That work seems to be tracked here, #42743. The following cannot be used as operands for inline asm: * `r2`: the TOC pointer, required for most PIC code. * `r13`: the TLS pointer * `r[29]`: Reserved for internal usage by LLVM on PowerPC * `r[30]`: Reserved for internal usage by LLVM on PowerPC and PowerPC64 * `r31`: the frame pointer * `vrsave`: this is effectively an unused special-purpose register. The `preserves_flags` behavior is updated with the following behavior (Note, this is not enforceable today due to LLVM restrictions): * All status and sticky bits of `fpscr`, `spefscr`, and `vscr` are preserved. The following registers are unavailable: * `mma[0-7]`: These are new "registers" available on Power10, they are 512b registers which overlay 4x vsx registers. If needed, users can mark such clobbers as vsN*4, vsN*4+1,...,vsN*4+3. * `ap`: This is actually a pseudo-register in gcc/llvm. * `mq`: This register is only available on Power1 and Power2, and is not supported by llvm. --- cc @taiki-e r? @Amanieu @rustbot label +A-inline-assembly
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‎compiler/rustc_ast_lowering/src/asm.rs‎

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@@ -51,6 +51,8 @@ impl<'a, 'hir> LoweringContext<'a, 'hir> {
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| asm::InlineAsmArch::LoongArch32
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| asm::InlineAsmArch::LoongArch64
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| asm::InlineAsmArch::S390x
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| asm::InlineAsmArch::PowerPC
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| asm::InlineAsmArch::PowerPC64
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);
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if !is_stable
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&& !self.tcx.features().asm_experimental_arch()

‎src/doc/unstable-book/src/language-features/asm-experimental-arch.md‎

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@@ -8,7 +8,6 @@ The tracking issue for this feature is: [#93335]
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This feature tracks `asm!` and `global_asm!` support for the following architectures:
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- NVPTX
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- PowerPC
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- Hexagon
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- MIPS32r2 and MIPS64r2
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- wasm32
@@ -31,16 +30,6 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
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| NVPTX | `reg64` | None\* | `l` |
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| Hexagon | `reg` | `r[0-28]` | `r` |
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| Hexagon | `preg` | `p[0-3]` | Only clobbers |
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| PowerPC | `reg` | `r0`, `r[3-12]`, `r[14-29]`\* | `r` |
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| PowerPC | `reg_nonzero` | `r[3-12]`, `r[14-29]`\* | `b` |
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| PowerPC | `freg` | `f[0-31]` | `f` |
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| PowerPC | `vreg` | `v[0-31]` | `v` |
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| PowerPC | `vsreg | `vs[0-63]` | `wa` |
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| PowerPC | `cr` | `cr[0-7]`, `cr` | Only clobbers |
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| PowerPC | `ctr` | `ctr` | Only clobbers |
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| PowerPC | `lr` | `lr` | Only clobbers |
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| PowerPC | `xer` | `xer` | Only clobbers |
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| PowerPC | `spe_acc` | `spe_acc` | Only clobbers |
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| wasm32 | `local` | None\* | `r` |
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| BPF | `reg` | `r[0-10]` | `r` |
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| BPF | `wreg` | `w[0-10]` | `w` |
@@ -62,10 +51,6 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
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> - NVPTX doesn't have a fixed register set, so named registers are not supported.
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>
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> - WebAssembly doesn't have registers, so named registers are not supported.
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>
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> - r29 is reserved only on 32 bit PowerPC targets.
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>
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> - spe_acc is only available on PowerPC SPE targets.
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# Register class supported types
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@@ -80,17 +65,6 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
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| NVPTX | `reg64` | None | `i8`, `i16`, `i32`, `f32`, `i64`, `f64` |
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| Hexagon | `reg` | None | `i8`, `i16`, `i32`, `f32` |
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| Hexagon | `preg` | N/A | Only clobbers |
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| PowerPC | `reg` | None | `i8`, `i16`, `i32`, `i64` (powerpc64 only) |
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| PowerPC | `reg_nonzero` | None | `i8`, `i16`, `i32`, `i64` (powerpc64 only) |
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| PowerPC | `freg` | None | `f32`, `f64` |
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| PowerPC | `vreg` | `altivec` | `i8x16`, `i16x8`, `i32x4`, `f32x4` |
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| PowerPC | `vreg` | `vsx` | `f32`, `f64`, `i64x2`, `f64x2` |
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| PowerPC | `vsreg` | `vsx` | The union of vsx and altivec vreg types |
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| PowerPC | `cr` | N/A | Only clobbers |
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| PowerPC | `ctr` | N/A | Only clobbers |
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| PowerPC | `lr` | N/A | Only clobbers |
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| PowerPC | `xer` | N/A | Only clobbers |
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| PowerPC | `spe_acc` | N/A | Only clobbers |
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| wasm32 | `local` | None | `i8` `i16` `i32` `i64` `f32` `f64` |
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| BPF | `reg` | None | `i8` `i16` `i32` `i64` |
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| BPF | `wreg` | `alu32` | `i8` `i16` `i32` |
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| Hexagon | `r29` | `sp` |
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| Hexagon | `r30` | `fr` |
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| Hexagon | `r31` | `lr` |
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| PowerPC | `r1` | `sp` |
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| PowerPC | `r31` | `fp` |
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| PowerPC | `r[0-31]` | `[0-31]` |
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| PowerPC | `f[0-31]` | `fr[0-31]`|
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| BPF | `r[0-10]` | `w[0-10]` |
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| AVR | `XH` | `r27` |
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| AVR | `XL` | `r26` |
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| Architecture | Unsupported register | Reason |
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| ------------ | --------------------------------------- | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
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| All | `sp`, `r14`/`o6` (SPARC) | The stack pointer must be restored to its original value at the end of an asm code block. |
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| All | `fr` (Hexagon), `fp` (PowerPC), `$fp` (MIPS), `Y` (AVR), `r4` (MSP430), `a6` (M68k), `r30`/`i6` (SPARC) | The frame pointer cannot be used as an input or output. |
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| All | `r19` (Hexagon), `r29` (PowerPC 32 bit only), `r30` (PowerPC) | These are used internally by LLVM as "base pointer" for functions with complex stack frames. |
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| All | `fr` (Hexagon) `$fp` (MIPS), `Y` (AVR), `r4` (MSP430), `a6` (M68k), `r30`/`i6` (SPARC) | The frame pointer cannot be used as an input or output. |
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| All | `r19` (Hexagon) | These are used internally by LLVM as "base pointer" for functions with complex stack frames. |
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| MIPS | `$0` or `$zero` | This is a constant zero register which can't be modified. |
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| MIPS | `$1` or `$at` | Reserved for assembler. |
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| MIPS | `$26`/`$k0`, `$27`/`$k1` | OS-reserved registers. |
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| MIPS | `$28`/`$gp` | Global pointer cannot be used as inputs or outputs. |
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| MIPS | `$ra` | Return address cannot be used as inputs or outputs. |
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| Hexagon | `lr` | This is the link register which cannot be used as an input or output. |
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| PowerPC | `r2`, `r13` | These are system reserved registers. |
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| PowerPC | `vrsave` | The vrsave register cannot be used as an input or output. |
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| AVR | `r0`, `r1`, `r1r0` | Due to an issue in LLVM, the `r0` and `r1` registers cannot be used as inputs or outputs. If modified, they must be restored to their original values before the end of the block. |
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|MSP430 | `r0`, `r2`, `r3` | These are the program counter, status register, and constant generator respectively. Neither the status register nor constant generator can be written to. |
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| M68k | `a4`, `a5` | Used internally by LLVM for the base pointer and global base pointer. |
@@ -189,11 +157,6 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
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| NVPTX | `reg32` | None | `r0` | None |
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| NVPTX | `reg64` | None | `rd0` | None |
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| Hexagon | `reg` | None | `r0` | None |
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| PowerPC | `reg` | None | `0` | None |
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| PowerPC | `reg_nonzero` | None | `3` | None |
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| PowerPC | `freg` | None | `0` | None |
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| PowerPC | `vreg` | None | `0` | None |
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| PowerPC | `vsreg` | None | `0` | None |
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| SPARC | `reg` | None | `%o0` | None |
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| CSKY | `reg` | None | `r0` | None |
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| CSKY | `freg` | None | `f0` | None |

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