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Rollup merge of #135383 - BoxyUwU:cov_tag_ptr, r=compiler-errors
De-abstract tagged ptr and make it covariant In #135272 I needed to use a tagged ptr in `hir::TyKind` in order to not regress hir type sizes. Unfortunately the existing `CopyTaggedPtr` abstraction is insufficient as it makes the `'hir` lifetime invariant. I spent some time trying to keep existing functionality while making it covariant but in the end I realised that actually we dont use *any* of this code *anywhere* in rustc, so I've just removed everything and replaced it with a much less general abstraction that is suitable for what I need in #135272. Idk if anyone has a preference for just keeping all the abstractions here in case anyone needs them in the future 🤷‍♀️
2 parents 24cc0cb + 4de8cef commit fad3039

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compiler/rustc_data_structures/src/marker.rs

+2-2
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,7 @@ impl_dyn_send!(
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[Vec<T, A> where T: DynSend, A: std::alloc::Allocator + DynSend]
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[Box<T, A> where T: ?Sized + DynSend, A: std::alloc::Allocator + DynSend]
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[crate::sync::RwLock<T> where T: DynSend]
75-
[crate::tagged_ptr::CopyTaggedPtr<P, T, CP> where P: Send + crate::tagged_ptr::Pointer, T: Send + crate::tagged_ptr::Tag, const CP: bool]
75+
[crate::tagged_ptr::TaggedRef<'a, P, T> where 'a, P: Sync, T: Send + crate::tagged_ptr::Tag]
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[rustc_arena::TypedArena<T> where T: DynSend]
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[indexmap::IndexSet<V, S> where V: DynSend, S: DynSend]
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[indexmap::IndexMap<K, V, S> where K: DynSend, V: DynSend, S: DynSend]
@@ -148,7 +148,7 @@ impl_dyn_sync!(
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[crate::sync::RwLock<T> where T: DynSend + DynSync]
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[crate::sync::WorkerLocal<T> where T: DynSend]
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[crate::intern::Interned<'a, T> where 'a, T: DynSync]
151-
[crate::tagged_ptr::CopyTaggedPtr<P, T, CP> where P: Sync + crate::tagged_ptr::Pointer, T: Sync + crate::tagged_ptr::Tag, const CP: bool]
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[crate::tagged_ptr::TaggedRef<'a, P, T> where 'a, P: Sync, T: Sync + crate::tagged_ptr::Tag]
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[parking_lot::lock_api::Mutex<R, T> where R: DynSync, T: ?Sized + DynSend]
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[parking_lot::lock_api::RwLock<R, T> where R: DynSync, T: ?Sized + DynSend + DynSync]
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[indexmap::IndexSet<V, S> where V: DynSync, S: DynSync]

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