From 682a64d4ef7af063794748a2a90cd5c70a12b434 Mon Sep 17 00:00:00 2001 From: Richard-Rogalski Date: Sun, 7 May 2023 22:47:38 -0500 Subject: [PATCH 1/3] add ppc clobbers --- compiler/rustc_target/src/asm/mod.rs | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/compiler/rustc_target/src/asm/mod.rs b/compiler/rustc_target/src/asm/mod.rs index 705966f52370e..e452024004176 100644 --- a/compiler/rustc_target/src/asm/mod.rs +++ b/compiler/rustc_target/src/asm/mod.rs @@ -840,6 +840,7 @@ pub enum InlineAsmClobberAbi { AArch64NoX18, RiscV, LoongArch, + PowerPC, } impl InlineAsmClobberAbi { @@ -885,6 +886,10 @@ impl InlineAsmClobberAbi { "C" | "system" | "efiapi" => Ok(InlineAsmClobberAbi::LoongArch), _ => Err(&["C", "system", "efiapi"]), }, + InlineAsmArch::PowerPC => match name { + "C" | "system" | "efiapi" => Ok(InlineAsmClobberAbi::PowerPC), + _ => Err(&["C", "system", "efiapi"]), + }, _ => Err(&[]), } } @@ -1042,6 +1047,23 @@ impl InlineAsmClobberAbi { f16, f17, f18, f19, f20, f21, f22, f23, } }, + InlineAsmClobberAbi::PowerPC => clobbered_regs! { + PowerPC PowerPCInlineAsmReg { + // ra + r0, + // + r3, r4, r5, r6, r7, r8, r9, r10, + //r11, r12, + // float + f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, + f10, f11, f12, f13, + + // VMX capable only + //v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, + //v10, v11, v12, v13, v14, v15, v16, v17, + //v18, v19, + } + }, } } } From 42171d588ff795a29c1b85230d294bb6486d20c1 Mon Sep 17 00:00:00 2001 From: Richard-Rogalski Date: Thu, 11 May 2023 19:48:53 -0500 Subject: [PATCH 2/3] Add VSX, few other things --- compiler/rustc_codegen_llvm/src/asm.rs | 4 +++ compiler/rustc_target/src/asm/mod.rs | 12 ++++---- compiler/rustc_target/src/asm/powerpc.rs | 38 ++++++++++++++++++++++++ 3 files changed, 47 insertions(+), 7 deletions(-) diff --git a/compiler/rustc_codegen_llvm/src/asm.rs b/compiler/rustc_codegen_llvm/src/asm.rs index f9af103c9ad83..8c775c2e8527b 100644 --- a/compiler/rustc_codegen_llvm/src/asm.rs +++ b/compiler/rustc_codegen_llvm/src/asm.rs @@ -644,6 +644,7 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'_>>) -> InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg) => "r", InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg_nonzero) => "b", InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::freg) => "f", + InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::vreg) => "v", InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::cr) | InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::xer) => { unreachable!("clobber-only") @@ -817,6 +818,9 @@ fn dummy_output_type<'ll>(cx: &CodegenCx<'ll, '_>, reg: InlineAsmRegClass) -> &' InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg) => cx.type_i32(), InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg_nonzero) => cx.type_i32(), InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::freg) => cx.type_f64(), + InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::vreg) => cx.type_vector(cx.type_i64(), 2),//no clue if this is right :D + //All PPC vreg's are 128-bits wide. + //Each vreg can hold sixteen 8-bit elements, eight 16-bit elements, or four 32-bit elements. InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::cr) | InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::xer) => { unreachable!("clobber-only") diff --git a/compiler/rustc_target/src/asm/mod.rs b/compiler/rustc_target/src/asm/mod.rs index e452024004176..899d115aade7a 100644 --- a/compiler/rustc_target/src/asm/mod.rs +++ b/compiler/rustc_target/src/asm/mod.rs @@ -886,7 +886,7 @@ impl InlineAsmClobberAbi { "C" | "system" | "efiapi" => Ok(InlineAsmClobberAbi::LoongArch), _ => Err(&["C", "system", "efiapi"]), }, - InlineAsmArch::PowerPC => match name { + InlineAsmArch::PowerPC | InlineAsmArch::PowerPC64 => match name { "C" | "system" | "efiapi" => Ok(InlineAsmClobberAbi::PowerPC), _ => Err(&["C", "system", "efiapi"]), }, @@ -1051,17 +1051,15 @@ impl InlineAsmClobberAbi { PowerPC PowerPCInlineAsmReg { // ra r0, - // - r3, r4, r5, r6, r7, r8, r9, r10, - //r11, r12, + r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, // float f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, // VMX capable only - //v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, - //v10, v11, v12, v13, v14, v15, v16, v17, - //v18, v19, + v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, + v10, v11, v12, v13, v14, v15, v16, v17, + v18, v19, } }, } diff --git a/compiler/rustc_target/src/asm/powerpc.rs b/compiler/rustc_target/src/asm/powerpc.rs index d3ccb30350a27..5b4ec3a3b9f15 100644 --- a/compiler/rustc_target/src/asm/powerpc.rs +++ b/compiler/rustc_target/src/asm/powerpc.rs @@ -8,6 +8,7 @@ def_reg_class! { reg, reg_nonzero, freg, + vreg, cr, xer, } @@ -47,6 +48,7 @@ impl PowerPCInlineAsmRegClass { } } Self::freg => types! { _: F32, F64; }, + Self::vreg => todo!(),//not quite sure :) Self::cr | Self::xer => &[], } } @@ -112,6 +114,38 @@ def_regs! { f29: freg = ["f29", "fr29"], f30: freg = ["f30", "fr30"], f31: freg = ["f31", "fr31"], + v0: vreg = ["v0"], + v1: vreg = ["v1"], + v2: vreg = ["v2"], + v3: vreg = ["v3"], + v4: vreg = ["v4"], + v5: vreg = ["v5"], + v6: vreg = ["v6"], + v7: vreg = ["v7"], + v8: vreg = ["v8"], + v9: vreg = ["v9"], + v10: vreg = ["v10"], + v11: vreg = ["v11"], + v12: vreg = ["v12"], + v13: vreg = ["v13"], + v14: vreg = ["v14"], + v15: vreg = ["v15"], + v16: vreg = ["v16"], + v17: vreg = ["v17"], + v18: vreg = ["v18"], + v19: vreg = ["v19"], + v20: vreg = ["v20"], + v21: vreg = ["v21"], + v22: vreg = ["v22"], + v23: vreg = ["v23"], + v24: vreg = ["v24"], + v25: vreg = ["v25"], + v26: vreg = ["v26"], + v27: vreg = ["v27"], + v28: vreg = ["v28"], + v29: vreg = ["v29"], + v30: vreg = ["v30"], + v31: vreg = ["v31"], cr: cr = ["cr"], cr0: cr = ["cr0"], cr1: cr = ["cr1"], @@ -169,6 +203,10 @@ impl PowerPCInlineAsmReg { (f8, "8"), (f9, "9"), (f10, "10"), (f11, "11"), (f12, "12"), (f13, "13"), (f14, "14"), (f15, "15"); (f16, "16"), (f17, "17"), (f18, "18"), (f19, "19"), (f20, "20"), (f21, "21"), (f22, "22"), (f23, "23"); (f24, "24"), (f25, "25"), (f26, "26"), (f27, "27"), (f28, "28"), (f29, "29"), (f30, "30"), (f31, "31"); + (v0, "0"), (v1, "1"), (v2, "2"), (v3, "3"), (v4, "4"), (v5, "5"), (v6, "6"), (v7, "7"); + (v8, "8"), (v9, "9"), (v10, "10"), (v11, "11"), (v12, "12"), (v13, "13"), (v14, "14"), (v15, "15"); + (v16, "16"), (v17, "17"), (v18, "18"), (v19, "19"), (v20, "20"), (v21, "21"), (v22, "22"), (v23, "23"); + (v24, "24"), (v25, "25"), (v26, "26"), (v27, "27"), (v28, "28"), (v29, "29"), (v30, "30"), (v31, "31"); (cr, "cr"); (cr0, "0"), (cr1, "1"), (cr2, "2"), (cr3, "3"), (cr4, "4"), (cr5, "5"), (cr6, "6"), (cr7, "7"); (xer, "xer"); From 802029c01bbfec0242d2c5e4fe908a64dcaeb5de Mon Sep 17 00:00:00 2001 From: Richard-Rogalski Date: Fri, 12 May 2023 00:01:11 -0500 Subject: [PATCH 3/3] Format, fix build failures --- compiler/rustc_codegen_gcc/src/asm.rs | 4 +++- compiler/rustc_codegen_llvm/src/asm.rs | 9 ++++++--- compiler/rustc_target/src/asm/powerpc.rs | 4 ++-- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/compiler/rustc_codegen_gcc/src/asm.rs b/compiler/rustc_codegen_gcc/src/asm.rs index 250aa79f8d609..3c0317ab90ee1 100644 --- a/compiler/rustc_codegen_gcc/src/asm.rs +++ b/compiler/rustc_codegen_gcc/src/asm.rs @@ -610,7 +610,8 @@ fn reg_to_gcc(reg: InlineAsmRegOrRegClass) -> ConstraintOrRegister { InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg) => "r", InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg_nonzero) => "b", InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::freg) => "f", - InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::cr) + InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::vreg) => "v", + InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::cr)//should this not be either x or y ? | InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::xer) => { unreachable!("clobber-only") }, @@ -683,6 +684,7 @@ fn dummy_output_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, reg: InlineAsmRegCl InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg) => cx.type_i32(), InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg_nonzero) => cx.type_i32(), InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::freg) => cx.type_f64(), + InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::vreg) => cx.type_vector(cx.type_i64(), 2), InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::cr) | InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::xer) => { unreachable!("clobber-only") diff --git a/compiler/rustc_codegen_llvm/src/asm.rs b/compiler/rustc_codegen_llvm/src/asm.rs index 8c775c2e8527b..46377eea9ff1a 100644 --- a/compiler/rustc_codegen_llvm/src/asm.rs +++ b/compiler/rustc_codegen_llvm/src/asm.rs @@ -818,9 +818,12 @@ fn dummy_output_type<'ll>(cx: &CodegenCx<'ll, '_>, reg: InlineAsmRegClass) -> &' InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg) => cx.type_i32(), InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg_nonzero) => cx.type_i32(), InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::freg) => cx.type_f64(), - InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::vreg) => cx.type_vector(cx.type_i64(), 2),//no clue if this is right :D - //All PPC vreg's are 128-bits wide. - //Each vreg can hold sixteen 8-bit elements, eight 16-bit elements, or four 32-bit elements. + InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::vreg) => { + cx.type_vector(cx.type_i64(), 2) + } //no clue if this is right :D + // IBM doc: All PPC vreg's are 128-bits wide. + //Each vreg can hold sixteen 8-bit elements, eight 16-bit elements, or four 32-bit elements. + // LLVM doc: For 4 x f32 or 4 x f64 types, a 128-bit altivec vector InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::cr) | InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::xer) => { unreachable!("clobber-only") diff --git a/compiler/rustc_target/src/asm/powerpc.rs b/compiler/rustc_target/src/asm/powerpc.rs index 5b4ec3a3b9f15..f266abea1a72c 100644 --- a/compiler/rustc_target/src/asm/powerpc.rs +++ b/compiler/rustc_target/src/asm/powerpc.rs @@ -8,7 +8,7 @@ def_reg_class! { reg, reg_nonzero, freg, - vreg, + vreg, cr, xer, } @@ -48,7 +48,7 @@ impl PowerPCInlineAsmRegClass { } } Self::freg => types! { _: F32, F64; }, - Self::vreg => todo!(),//not quite sure :) + Self::vreg => todo!(), //not quite sure :) Self::cr | Self::xer => &[], } }