From adb92aeb4a1f6cd8313fa880c19a39a8caefbded Mon Sep 17 00:00:00 2001 From: Tsukasa OI Date: Wed, 30 Apr 2025 05:48:51 +0000 Subject: [PATCH 1/3] rustc_target: Adjust RISC-V feature implication (Za64rs and Za128rs) The Za64rs extension (reservation set -- a primitive memory unit of LR/SC atomic operations -- is naturally aligned and *at most* 64 bytes) is a superset of the Za128rs extension (*at most* 128 bytes; note that smaller the reservation set is, more fine grained control over atomics). This commit handles this as a feature implication. --- compiler/rustc_target/src/target_features.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/rustc_target/src/target_features.rs b/compiler/rustc_target/src/target_features.rs index 69c8b9119ab23..9031e0530c583 100644 --- a/compiler/rustc_target/src/target_features.rs +++ b/compiler/rustc_target/src/target_features.rs @@ -507,7 +507,7 @@ static RISCV_FEATURES: &[(&str, Stability, ImpliedFeatures)] = &[ ("unaligned-vector-mem", Unstable(sym::riscv_target_feature), &[]), ("v", Unstable(sym::riscv_target_feature), &["zvl128b", "zve64d"]), ("za128rs", Unstable(sym::riscv_target_feature), &[]), - ("za64rs", Unstable(sym::riscv_target_feature), &[]), + ("za64rs", Unstable(sym::riscv_target_feature), &["za128rs"]), // Za64rs ⊃ Za128rs ("zaamo", Unstable(sym::riscv_target_feature), &[]), ("zabha", Unstable(sym::riscv_target_feature), &["zaamo"]), ("zacas", Unstable(sym::riscv_target_feature), &["zaamo"]), From c6ed7869a13194748653f48350225bc9e0ced2ca Mon Sep 17 00:00:00 2001 From: Tsukasa OI Date: Wed, 30 Apr 2025 06:05:41 +0000 Subject: [PATCH 2/3] rustc_target: RISC-V: Add atomics/memory-related extensions This commit adds a part of RISC-V extensions that are mandatory part of the RVA23U64 profile (application-class processor profile) and related to memory/atomic constraints. The Zic64b extension constrains the cache line to naturally-aligned 64 bytes that would make certain memory operations (like zeroing the memory using the Zicboz extension) easier. The Zicbom and Zicbop extensions enable managing cache block-based operations (the Zicbop contains hints that will work as a NOP when this extension is absent and the Zicbom contains control instructions). Of which, the Zicbom extension is going to be discoverable from the Linux kernel (as of the version 6.15-rc4) and this commit prepares for corresponding stdarch changes. The Zicc* extensions add certain constraints to "the main memory" (usually true on the user mode application on the application-class processor but those extensions make sure such constraints exist). --- compiler/rustc_target/src/target_features.rs | 7 +++++++ tests/ui/check-cfg/target_feature.stderr | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/compiler/rustc_target/src/target_features.rs b/compiler/rustc_target/src/target_features.rs index 9031e0530c583..99f39b34b6298 100644 --- a/compiler/rustc_target/src/target_features.rs +++ b/compiler/rustc_target/src/target_features.rs @@ -531,7 +531,14 @@ static RISCV_FEATURES: &[(&str, Stability, ImpliedFeatures)] = &[ ("zfinx", Unstable(sym::riscv_target_feature), &["zicsr"]), ("zhinx", Unstable(sym::riscv_target_feature), &["zhinxmin"]), ("zhinxmin", Unstable(sym::riscv_target_feature), &["zfinx"]), + ("zic64b", Unstable(sym::riscv_target_feature), &[]), + ("zicbom", Unstable(sym::riscv_target_feature), &[]), + ("zicbop", Unstable(sym::riscv_target_feature), &[]), ("zicboz", Unstable(sym::riscv_target_feature), &[]), + ("ziccamoa", Unstable(sym::riscv_target_feature), &[]), + ("ziccif", Unstable(sym::riscv_target_feature), &[]), + ("zicclsm", Unstable(sym::riscv_target_feature), &[]), + ("ziccrse", Unstable(sym::riscv_target_feature), &[]), ("zicntr", Unstable(sym::riscv_target_feature), &["zicsr"]), ("zicond", Unstable(sym::riscv_target_feature), &[]), ("zicsr", Unstable(sym::riscv_target_feature), &[]), diff --git a/tests/ui/check-cfg/target_feature.stderr b/tests/ui/check-cfg/target_feature.stderr index 4f7b8345e86ad..1740587735499 100644 --- a/tests/ui/check-cfg/target_feature.stderr +++ b/tests/ui/check-cfg/target_feature.stderr @@ -329,7 +329,14 @@ LL | cfg!(target_feature = "_UNEXPECTED_VALUE"); `zfinx` `zhinx` `zhinxmin` +`zic64b` +`zicbom` +`zicbop` `zicboz` +`ziccamoa` +`ziccif` +`zicclsm` +`ziccrse` `zicntr` `zicond` `zicsr` From 501a539bbe74164384ebf42165b058bc01f6b5a2 Mon Sep 17 00:00:00 2001 From: Tsukasa OI Date: Wed, 30 Apr 2025 06:53:22 +0000 Subject: [PATCH 3/3] rustc_target: RISC-V: Add BF16 extensions This commit adds three ratified unprivileged RISC-V extensions related to BFloat16 (BF16) handling. Although that they are far from stabilization due to ABI issues, they are optional extensions of the RVA23U64 profile (application-class processor profile) and going to be discoverable from the Linux kernel (as of version 6.15-rc4). This commit mainly prepares runtime detection of those extensions. --- compiler/rustc_target/src/target_features.rs | 3 +++ tests/ui/check-cfg/target_feature.stderr | 3 +++ 2 files changed, 6 insertions(+) diff --git a/compiler/rustc_target/src/target_features.rs b/compiler/rustc_target/src/target_features.rs index 99f39b34b6298..009118f2d4ff4 100644 --- a/compiler/rustc_target/src/target_features.rs +++ b/compiler/rustc_target/src/target_features.rs @@ -526,6 +526,7 @@ static RISCV_FEATURES: &[(&str, Stability, ImpliedFeatures)] = &[ ("zcmop", Unstable(sym::riscv_target_feature), &["zca"]), ("zdinx", Unstable(sym::riscv_target_feature), &["zfinx"]), ("zfa", Unstable(sym::riscv_target_feature), &["f"]), + ("zfbfmin", Unstable(sym::riscv_target_feature), &["f"]), // and a subset of Zfhmin ("zfh", Unstable(sym::riscv_target_feature), &["zfhmin"]), ("zfhmin", Unstable(sym::riscv_target_feature), &["f"]), ("zfinx", Unstable(sym::riscv_target_feature), &["zicsr"]), @@ -565,6 +566,8 @@ static RISCV_FEATURES: &[(&str, Stability, ImpliedFeatures)] = &[ ("zve64d", Unstable(sym::riscv_target_feature), &["zve64f", "d"]), ("zve64f", Unstable(sym::riscv_target_feature), &["zve32f", "zve64x"]), ("zve64x", Unstable(sym::riscv_target_feature), &["zve32x", "zvl64b"]), + ("zvfbfmin", Unstable(sym::riscv_target_feature), &["zve32f"]), + ("zvfbfwma", Unstable(sym::riscv_target_feature), &["zfbfmin", "zvfbfmin"]), ("zvfh", Unstable(sym::riscv_target_feature), &["zvfhmin", "zve32f", "zfhmin"]), // Zvfh ⊃ Zvfhmin ("zvfhmin", Unstable(sym::riscv_target_feature), &["zve32f"]), ("zvkb", Unstable(sym::riscv_target_feature), &["zve32x"]), diff --git a/tests/ui/check-cfg/target_feature.stderr b/tests/ui/check-cfg/target_feature.stderr index 1740587735499..712ce941c54ce 100644 --- a/tests/ui/check-cfg/target_feature.stderr +++ b/tests/ui/check-cfg/target_feature.stderr @@ -324,6 +324,7 @@ LL | cfg!(target_feature = "_UNEXPECTED_VALUE"); `zcmop` `zdinx` `zfa` +`zfbfmin` `zfh` `zfhmin` `zfinx` @@ -363,6 +364,8 @@ LL | cfg!(target_feature = "_UNEXPECTED_VALUE"); `zve64d` `zve64f` `zve64x` +`zvfbfmin` +`zvfbfwma` `zvfh` `zvfhmin` `zvkb`