increase feature cache size

Author: gnzlbg

coresimd/src/lib.rs

@@ -13,7 +13,7 @@
 #![allow(unused_features)]
 #![feature(const_fn, link_llvm_intrinsics, platform_intrinsics, repr_simd,
            simd_ffi, target_feature, cfg_target_feature, i128_type, asm,
-           const_atomic_usize_new, stmt_expr_attributes, core_intrinsics,
+           integer_atomics, stmt_expr_attributes, core_intrinsics,
            crate_in_paths)]
 #![cfg_attr(test, feature(proc_macro, test, attr_literals))]
 #![cfg_attr(feature = "cargo-clippy",

coresimd/src/runtime/aarch64.rs

@@ -1,6 +1,6 @@
 //! Run-time feature detection on ARM Aarch64.
-use runtime::bit;
 use runtime::arch::HasFeature;
+use runtime::cache;
 
 #[macro_export]
 #[doc(hidden)]
@@ -32,12 +32,12 @@ pub enum __Feature {
     pmull,
 }
 
-pub fn detect_features<T: HasFeature>(mut x: T) -> usize {
-    let mut value: usize = 0;
+pub fn detect_features<T: HasFeature>(mut x: T) -> cache::Initializer {
+    let mut value = cache::Initializer::new();
     {
         let mut enable_feature = |f| {
             if x.has_feature(&f) {
-                value = bit::set(value, f as u32);
+                value.set(f as u32);
             }
         };
         enable_feature(__Feature::asimd);

coresimd/src/runtime/arm.rs

@@ -1,5 +1,5 @@
 //! Run-time feature detection on ARM Aarch32.
-use runtime::bit;
+use runtime::cache;
 use runtime::arch::HasFeature;
 
 #[macro_export]
@@ -28,12 +28,12 @@ pub enum __Feature {
     pmull,
 }
 
-pub fn detect_features<T: HasFeature>(mut x: T) -> usize {
-    let mut value: usize = 0;
+pub fn detect_features<T: HasFeature>(mut x: T) -> cache::Initializer {
+    let mut value = cache::Initializer::new();
     {
         let mut enable_feature = |f| {
             if x.has_feature(&f) {
-                value = bit::set(value, f as u32);
+                value.set(f as u32);
             }
         };
         enable_feature(__Feature::neon);

coresimd/src/runtime/bit.rs

@@ -1,30 +1,97 @@
-//! Cache of run-time feature detection
+//! Caches run-time feature detection so that it only needs to be computed
+//! once.
 
-use core::sync::atomic::{AtomicUsize, Ordering};
+use core::sync::atomic::{AtomicU64, Ordering};
 
-use super::bit;
+/// Sets the `bit` of `x`.
+pub const fn set_bit(x: u64, bit: u32) -> u64 {
+    x | 1 << bit
+}
+
+/// Tests the `bit` of `x`.
+pub const fn test_bit(x: u64, bit: u32) -> bool {
+    x & (1 << bit) != 0
+}
+
+/// Maximum number of features that can be cached.
+const CACHE_CAPACITY: u32 = 63;
+
+/// This type is used to initialize the cache
+pub struct Initializer(u64);
+
+impl Initializer {
+    /// Creates a cleared cache.
+    pub fn new() -> Self {
+        Initializer(0)
+    }
+    /// Tests the `bit` of the cache.
+    pub fn test(&self, bit: u32) -> bool {
+        // FIXME: this way of making sure that the cache is large enough is
+        // brittle.
+        debug_assert!(
+            bit < CACHE_CAPACITY,
+            "too many features, time to increase the cache size!"
+        );
+        test_bit(self.0, bit)
+    }
+    /// Sets the `bit` of the cache.
+    pub fn set(&mut self, bit: u32) {
+        // FIXME: this way of making sure that the cache is large enough is
+        // brittle.
+        debug_assert!(
+            bit < CACHE_CAPACITY,
+            "too many features, time to increase the cache size!"
+        );
+        let v = self.0;
+        self.0 = set_bit(v, bit);
+    }
+}
 
-/// This global variable is a bitset used to cache the features supported by
-/// the
-/// CPU.
-static CACHE: AtomicUsize = AtomicUsize::new(usize::max_value());
+/// Feature cache with capacity for `CACHE_CAPACITY` features.
+///
+/// Note: the last feature bit is used to represent an
+/// uninitialized cache.
+struct Cache(AtomicU64);
+
+/// This global variable is a cache of the features supported by the CPU.
+static CACHE: Cache = Cache::uninitialized();
+
+impl Cache {
+    /// Creates an uninitialized cache.
+    const fn uninitialized() -> Self {
+        Cache(AtomicU64::new(u64::max_value()))
+    }
+    /// Is the cache uninitialized?
+    pub fn is_uninitialized(&self) -> bool {
+        self.0.load(Ordering::Relaxed) == u64::max_value()
+    }
+
+    /// Is the `bit` in the cache set?
+    pub fn test(&self, bit: u32) -> bool {
+        test_bit(CACHE.0.load(Ordering::Relaxed), bit)
+    }
+
+    pub fn set(&self, value: Initializer) {
+        self.0.store(value.0, Ordering::Relaxed);
+    }
+}
 
 /// Test the `bit` of the storage. If the storage has not been initialized,
 /// initializes it with the result of `f()`.
 ///
 /// On its first invocation, it detects the CPU features and caches them in the
-/// `FEATURES` global variable as an `AtomicUsize`.
+/// `FEATURES` global variable as an `AtomicU64`.
 ///
 /// It uses the `__Feature` variant to index into this variable as a bitset. If
 /// the bit is set, the feature is enabled, and otherwise it is disabled.
 ///
 /// PLEASE: do not use this, it is an implementation detail subject to change.
 pub fn test<F>(bit: u32, f: F) -> bool
 where
-    F: FnOnce() -> usize,
+    F: FnOnce() -> Initializer,
 {
-    if CACHE.load(Ordering::Relaxed) == usize::max_value() {
-        CACHE.store(f(), Ordering::Relaxed);
+    if CACHE.is_uninitialized() {
+        CACHE.set(f());
     }
-    bit::test(CACHE.load(Ordering::Relaxed), bit)
+    CACHE.test(bit)
 }

coresimd/src/runtime/cache.rs

@@ -1,5 +1,5 @@
 //! Run-time feature detection on PowerPC64.
-use runtime::bit;
+use runtime::cache;
 use runtime::arch::HasFeature;
 
 #[macro_export]
@@ -33,12 +33,12 @@ pub enum __Feature {
     power8,
 }
 
-pub fn detect_features<T: HasFeature>(mut x: T) -> usize {
-    let mut value: usize = 0;
+pub fn detect_features<T: HasFeature>(mut x: T) -> cache::Initializer {
+    let mut value = cache::Initializer::new();
     {
         let mut enable_feature = |f| {
             if x.has_feature(&f) {
-                value = bit::set(value, f as u32);
+                value.set(f as u32);
             }
         };
         enable_feature(__Feature::altivec);

coresimd/src/runtime/powerpc64.rs

@@ -18,7 +18,7 @@
 
 use core::mem;
 
-use super::bit;
+use super::{bit, cache};
 
 /// This macro maps the string-literal feature names to values of the
 /// `__Feature` enum at compile-time. The feature names used are the same as
@@ -261,10 +261,10 @@ pub enum __Feature {
 /// [wiki_cpuid]: https://en.wikipedia.org/wiki/CPUID
 /// [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
 /// [amd64_ref]: http://support.amd.com/TechDocs/24594.pdf
-pub fn detect_features() -> usize {
+pub fn detect_features() -> cache::Initializer {
     use vendor::{__cpuid, __cpuid_count, has_cpuid, CpuidResult};
     use vendor::_xgetbv;
-    let mut value: usize = 0;
+    let mut value = cache::Initializer::new();
 
     // If the x86 CPU does not support the CPUID instruction then it is too
     // old to support any of the currently-detectable features.
@@ -340,7 +340,7 @@ pub fn detect_features() -> usize {
         // borrows value till the end of this scope:
         let mut enable = |r, rb, f| {
             if bit::test(r as usize, rb) {
-                value = bit::set(value, f as u32);
+                value.set(f as u32);
             }
         };