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Merge branch 'master' of github.com:schoeberl/wildcat
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README.md

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@@ -48,7 +48,7 @@ accepted at [ARCS 2025](https://arcs-conference.org/home).
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Prerequisit for this project is a working installation of
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the RISC-V tools. Chances are high that you can install
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them with your packet manager (see below).
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them with your package manager (see below).
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Wildcat is written in [Chisel](https://www.chisel-lang.org/).
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Therefore, you need a for Java, best installed with [SDKMAN](https://sdkman.io/),
@@ -60,9 +60,10 @@ and for the Artix 7 based Nexys A7.
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To start with Wildcat either fork the project or clone it from here with:
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git clone https://github.com/schoeberl/wildcat
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cd wildcat
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git submodule update --init --recursive
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```
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git clone --recursive https://github.com/schoeberl/wildcat
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cd wildcat
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```
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Here you can start the ISA simulator executing a simple program with
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@@ -124,14 +125,14 @@ make test
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Here are resource and fmax results for the 3-, 4-, and 5-stages pipeline.
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We exclude instruction and data memory/cache in the numbers.
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Cyclon IV has 4-bit LUTs and the timing info
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Cyclone IV has 4-bit LUTs and the timing info
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is for the Slow 1200mV 85C Model.
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Artix 7 has 6-bit LUTs.
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Skywater130 timing info is for max_tt_025C_1v80.
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| Design (Cyclon IV) | Fmax | LEs | Regs | RAM bits |
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| Design (Cyclone IV) | Fmax | LEs | Regs | RAM bits |
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|:---------------------------|:---------|:------|:------|:---------|
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| Three stages (regfile FF) | 80.2 MHz | 3,130 | 1,295 | 0 |
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| Three stages (regfile mem) | 86.2 MHz | 1,756 | 379 | 2,048 |
@@ -169,38 +170,40 @@ RAMs is zero.
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### Tools on MacOS
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Use brew to install gcc:
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Use [Mac Homebrew](https://brew.sh/) to install the Chisel and RISC-V tools:
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```
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brew install sbt riscv64-elf-binutils
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```
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The below was an older version. Still valid?
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```
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brew tap riscv-software-src/riscv
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brew install riscv-gnu-toolchain --with-NOmultilib
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```
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### Tools on Ubuntu:
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Should be best installed with apt-get:
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sudo apt-get install -y gcc-riscv64-unknown-elf
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```
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sudo apt-get install -y gcc-riscv64-unknown-elf
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```
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#### Build from source
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If you want to compiler them from source, here are some notes:
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If you want to compiler them from source, here are some notes (this
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really shouldn't be necessary on most platforms):
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sudo apt-get install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc
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git clone https://github.com/riscv/riscv-tools.git
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cd riscv-tools
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git submodule update --init --recursive
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export RISCV=$HOME/riscv-tools/local
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./build.sh
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```
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sudo apt-get install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc
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git clone https://github.com/riscv/riscv-tools.git
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cd riscv-tools
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git submodule update --init --recursive
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export RISCV=$HOME/riscv-tools/local
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./build.sh
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```
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Then add the tools to your PATH in .bashrc or .profile with:
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export PATH=$PATH:$HOME/riscv-tools/local/bin
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```
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export PATH=$PATH:$HOME/riscv-tools/local/bin
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```
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See also: [RISC-V Ubuntu Setup](https://github.com/schoeberl/cae-lab#vm-and-tool-installation)
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@@ -221,7 +224,7 @@ Here a list of project that could be a BSc, an MSc, a special course, an AdvCA p
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* Tapeout
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- Tiny Tapeout
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- Edu4Chip
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- efabless
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- efabless (R.I.P.)
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* Rust and WCET analysis
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* ISA extensions
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* Comparing RISC-V cores (start from https://dl-acm-org.proxy.findit.cvt.dk/doi/pdf/10.1145/3457388.3458657)
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- floating point emulation
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- compressed instructions
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* Interrupts and interrupt controller
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* G extension
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* floating-point unit
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* G extension (= Multiply M, Atomics A, and Floating point FD)
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* Compare Ibex, Wildcat, and a third RISC-V core
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* Towards booting uLinux and full Linux
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* SoC stuff: interconnect, peripherals, ...
@@ -263,30 +266,30 @@ prerequisite for running embedded Rust using the ISA simulator.
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Once ```rustup``` has been installed, the following components should be added by executing the following commands:
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#### Target for RV32I
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- ```rustup target add riscv32i-unknown-none-elf```
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- `rustup target add riscv32i-unknown-none-elf`
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##### LLVM tools
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- ```rustup component add llvm-tools-preview```
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- ```cargo install cargo-binutils```
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- `rustup component add llvm-tools-preview`
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- `cargo install cargo-binutils`
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### Getting started
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Currently, a simple starter project has been setup at [rust/starter-project](rust/starter-project).
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To compile and run the starter project with the ISA simulator,
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execute the following command from the root of the Wildcat project:
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- ```make rust-compile``` (compiles)
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- ```make rust-run``` (executes)
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- `make rust-compile` (compiles)
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- `make rust-run` (executes)
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Furthermore, the disassembly can be viewed by executing the following command:
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- ```make rust-disassemble``` (prints disassembly)
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- `make rust-disassemble` (prints disassembly)
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### Creating new Rust projects
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To maintain an organized project structure, a new Rust project can be created by executing the following command
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from the root of the Wildcat project:
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- ```cargo new rust/[YOUR_PROJECT_NAME] --vcs=none```
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- `cargo new rust/[YOUR_PROJECT_NAME] --vcs=none`
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To compile and run the new project with the ISA simulator,
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execute the following command from the root of the Wildcat project:
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- ```make rust-compile RUST_PROJECT=[YOUR_PROJECT_NAME]``` (compiles target project)
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- ```make rust-run RUST_PROJECT=[YOUR_PROJECT_NAME]``` (executes target project)
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- `make rust-compile RUST_PROJECT=[YOUR_PROJECT_NAME]` (compiles target project)
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- `make rust-run RUST_PROJECT=[YOUR_PROJECT_NAME]` (executes target project)
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Furthermore, the disassembly for the new project can be viewed by executing the following command:
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- ```make rust-disassembly``` (prints disassembly)
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- `make rust-disassembly` (prints disassembly)

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