Fix reset and the initial instruction for the ROM

Author: schoeberl

doc/README.md

@@ -13,6 +13,15 @@ Some notes collected along exploring RISC-V.
  * 4 stages: standard without the WB
  * 5 stages: mostly useless WB (just a Mux)
 
+## Reset
+
+ASIC memories with an input register have a random address value in the first clock cycle.
+Therefore, the first instruction shall not be executed.
+The instruction memory (SPM or cache) shall assert stall on this initial cycle, and Wildcat will substitute the instruction with a NOP.
+Stalling keeps the PC constant, therefore we can reset it to 0 (and not -4).
+
+Caches on a miss assert stall as well.
+
 ## Notes, Ideas
 
  * LUI could be recoded as ADDI with R0

doc/TODO.md

@@ -3,21 +3,23 @@
  * [ ] Write documentation
  * [ ] Change memory interface to `PipeCon`
  * [ ] Have a better drawing of `PipeCon` (in soc-comm)
- * [ ] why does // val pcReg = RegInit(-4.S(32.W).asUInt)  result in failing tests?
-   - [ ] Do not execute the first instruction from on-chip memory
-   - [ ] but start PC with -4
-   - [ ] remove initialization of the address register from the instruction ROM
+ * [x] why does // val pcReg = RegInit(-4.S(32.W).asUInt)  result in failing tests?
+   - [x] Do not execute the first instruction from on-chip memory
+   - [x] but start PC with -4
+   - [x] remove initialization of the address register from the instruction ROM
  * [ ] Something is fishy with testing, as SingleCycle works (even without branch)
  * [ ] Single cycle is not finished - tests are failing, disabled
- * [ ] Two tests fail with co-simulation when adding stall to fetch (the toggle)
+ * [x] Two tests fail with co-simulation when adding stall to fetch (the toggle)
  * [ ] Better names for signals (e.g., for those with feedback, e.g., RF write)
- * [ ] width.s should not fail in the ISA simulator
+ * [ ] width.s and string.s should not fail in the ISA simulator
     - [ ] string should work as well, do we need a linker script?
     - [ ] Work on failing simple tests (Simulator and Wildcat)
  * [ ] Start collecting information on other core interfaces (in my paper)
  * [ ] Make it super easy to see Wildcat in action, like in DrakRISCV
  * [ ] UART
  * [ ] Add caches
+ * [ ] I do not have a real CoSim test for the pipeline
+ * [ ] There are still three failing test with CA cosimlation
  * [ ] Have performance (PPA) as GitHub CI action
    - [ ] with a more useful external memory interface - instructions and data
  * [ ] Forwarding from ALU/memory to address computation is missing (missing a test?)

src/main/scala/wildcat/isasim/SimRV.scala

@@ -194,7 +194,6 @@ class SimRV(mem: Array[Int], start: Int, stop: Int) {
     def ecall(): Int = {
       funct3 match {
         case ESYS => {
-          println("ecall")
           run = false
           return 0
         }

src/main/scala/wildcat/pipeline/InstructionROM.scala

@@ -8,14 +8,16 @@ import chisel3._
 class InstructionROM(code: Array[Int]) extends Module {
   val io = IO(Flipped(new InstrIO()))
 
-  // TODO: this should not be reset, as ASIC memories have no reset
-  // val addrReg = Reg(UInt(32.W))
-  val addrReg = RegInit(0.U(32.W))
+  // No reset, as ASIC memories have no reset
+  val addrReg = Reg(UInt(32.W))
   addrReg := io.address
   val instructions = VecInit(code.toIndexedSeq.map(_.S(32.W).asUInt))
   io.data := instructions(addrReg(31, 2))
-  // for checking two failing tests
+  // simulating cache misses
   val toggle = RegInit(false.B)
   toggle := !toggle
-  io.stall := false.B
+  // first instruction shall not be executed (random address register)
+  val firstReg = RegInit(true.B)
+  firstReg := false.B
+  io.stall := firstReg || false.B // add toggle
 }

src/main/scala/wildcat/pipeline/ThreeCats.scala

@@ -35,24 +35,16 @@ class ThreeCats() extends Wildcat() {
   }
   val exFwdReg = RegInit(0.U.asTypeOf(exFwd))
 
-  // PC generation
-  // the following should be correct, but 2 tests fail
-  // TODO: don't execute first instruction coming from memory
-  // val pcReg = RegInit(-4.S(32.W).asUInt)
-  val pcReg = RegInit(0.S(32.W).asUInt)
+  // PC generation, first (invalid) instruction will stall, so init with 0 is OK
+  val pcReg = RegInit(0.U(32.W))
   val pcNext = WireDefault(Mux(doBranch, branchTarget, pcReg + 4.U))
   pcReg := pcNext
   io.imem.address := pcNext
 
   // Fetch
   val instr = WireDefault(io.imem.data)
-  val firstClocReg = RegInit(false.B)
-  firstClocReg := true.B
-  when(firstClocReg) {
-    // instr := 0x00000013.U
-  }
   when (io.imem.stall) {
-    instr := 0x00000013.U
+    instr := 0x00000033.U
     pcNext := pcReg
   }
 

src/test/scala/wildcat/CACoSimTest.scala

@@ -12,9 +12,7 @@ import wildcat.isasim.SimRV
 class CACoSimTest extends AnyFlatSpec with ChiselScalatestTester {
 
   val files = Util.getSimpleTests("risc-v-lab/tests/simple")
-  // val failed = List("string.bin", "width.bin")
-  val failed = List("shift2.bin", "shift.bin", "recursive.bin", "branchcnt.bin", "branchmany.bin", "branchtrap.bin", "loop.bin","string.bin", "width.bin")
-
+  val failed = List("string.bin", "recursive.bin", "loop.bin")
 
   for (f <- files) {
     s"Simulation: CA co-simulatoin (simple) $f" should "pass" in {
@@ -24,13 +22,17 @@ class CACoSimTest extends AnyFlatSpec with ChiselScalatestTester {
         succeed
       } else {
         val sim = SimRV.runSimRV(f.toString())
-        test(new WildcatTestTop(f.getAbsolutePath)) {
+        test(new WildcatTestTop(f.getAbsolutePath)).withAnnotations(Seq(WriteVcdAnnotation)) {
           d => {
-            d.clock.step(100)
+            for (i <- 0 until 100) {
+              if (!d.io.stop.peekBoolean()) {
+                d.clock.step()
+              }
+            }
             for (i <- 0 until 32) {
               val r = d.io.regFile(i).peekInt().toInt
               val e = sim.reg(i)
-              assert(r == e, f"reg($i) = $r, expected $e")
+              assert(r == e, f"reg($i) = 0x${r.toHexString}, expected 0x${e.toHexString} at ${sim.pc % 4} in $f")
             }
           }
         }

wildcat.gtkw

@@ -1,121 +1,52 @@
 [*]
 [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
-[*] Wed Sep 18 21:21:41 2024
+[*] Tue Aug 26 09:30:05 2025
 [*]
-[dumpfile] "/Users/martin/source/wildcat/test_run_dir/Single_asmjals_should_pass/ThreeTestTop.vcd"
-[dumpfile_mtime] "Wed Sep 18 21:11:24 2024"
-[dumpfile_size] 40876
+[dumpfile] "/Users/martin/source/wildcat/test_run_dir/Simulation_CA_cosimulatoin_simple_riscvlabtestssimpleboolbin_should_pass/WildcatTestTop.vcd"
+[dumpfile_mtime] "Tue Aug 26 09:29:09 2025"
+[dumpfile_size] 55572
 [savefile] "/Users/martin/source/wildcat/wildcat.gtkw"
 [timestart] 0
-[size] 1576 948
+[size] 1336 600
 [pos] -1 -1
-*-4.372963 36 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-[treeopen] ThreeTestTop.
-[treeopen] ThreeTestTop.three.
-[treeopen] ThreeTestTop.three.dmem.
-[treeopen] ThreeTestTop.three.dmem.mem.
-[sst_width] 253
+*-4.905419 15 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] WildcatTestTop.
+[treeopen] WildcatTestTop.cpuTop.
+[sst_width] 255
 [signals_width] 394
 [sst_expanded] 1
 [sst_vpaned_height] 158
 @28
-ThreeTestTop.three.cpu.clock
-ThreeTestTop.three.cpu.reset
+WildcatTestTop.clock
+WildcatTestTop.reset
 @22
-ThreeTestTop.three.cpu.pcNext[31:0]
-ThreeTestTop.three.cpu.pcReg[31:0]
-ThreeTestTop.three.cpu.instrReg[31:0]
-@200
--
-@22
-ThreeTestTop.three.cpu.decExReg__rs1[4:0]
-ThreeTestTop.three.cpu.decExReg__rs2[4:0]
-ThreeTestTop.three.cpu.decExReg__rd[4:0]
+WildcatTestTop.io_regFile_0[31:0]
+WildcatTestTop.io_regFile_1[31:0]
+WildcatTestTop.io_regFile_2[31:0]
+WildcatTestTop.io_regFile_3[31:0]
+WildcatTestTop.io_regFile_4[31:0]
+WildcatTestTop.io_regFile_5[31:0]
+WildcatTestTop.io_regFile_6[31:0]
+WildcatTestTop.io_regFile_7[31:0]
+WildcatTestTop.io_regFile_8[31:0]
+WildcatTestTop.io_regFile_9[31:0]
+WildcatTestTop.io_regFile_10[31:0]
+WildcatTestTop.cpuTop.cpu.pcReg[31:0]
+WildcatTestTop.cpuTop.cpu.pcNext[31:0]
+WildcatTestTop.cpuTop.cpu.instr[31:0]
+WildcatTestTop.cpuTop.cpu.instrReg[31:0]
 @28
-ThreeTestTop.three.cpu.decExReg__valid
-ThreeTestTop.three.cpu.decExReg__decOut_isJal
-ThreeTestTop.three.cpu.decExReg__decOut_isJalr
-@22
-ThreeTestTop.three.cpu.decExReg__rs1Val[31:0]
-ThreeTestTop.three.cpu.decExReg__rs2Val[31:0]
-ThreeTestTop.three.cpu.debugRegs_1[31:0]
-ThreeTestTop.three.cpu.debugRegs_2[31:0]
-ThreeTestTop.three.cpu.debugRegs_3[31:0]
-ThreeTestTop.three.cpu.debugRegs_4[31:0]
-ThreeTestTop.three.cpu.debugRegs_5[31:0]
-ThreeTestTop.three.cpu.debugRegs_6[31:0]
-ThreeTestTop.three.cpu.debugRegs_7[31:0]
-@200
--
-@c00023
-ThreeTestTop.three.cpu.res[31:0]
-@29
-(0)ThreeTestTop.three.cpu.res[31:0]
-(1)ThreeTestTop.three.cpu.res[31:0]
-(2)ThreeTestTop.three.cpu.res[31:0]
-(3)ThreeTestTop.three.cpu.res[31:0]
-(4)ThreeTestTop.three.cpu.res[31:0]
-(5)ThreeTestTop.three.cpu.res[31:0]
-(6)ThreeTestTop.three.cpu.res[31:0]
-(7)ThreeTestTop.three.cpu.res[31:0]
-(8)ThreeTestTop.three.cpu.res[31:0]
-(9)ThreeTestTop.three.cpu.res[31:0]
-(10)ThreeTestTop.three.cpu.res[31:0]
-(11)ThreeTestTop.three.cpu.res[31:0]
-(12)ThreeTestTop.three.cpu.res[31:0]
-(13)ThreeTestTop.three.cpu.res[31:0]
-(14)ThreeTestTop.three.cpu.res[31:0]
-(15)ThreeTestTop.three.cpu.res[31:0]
-(16)ThreeTestTop.three.cpu.res[31:0]
-(17)ThreeTestTop.three.cpu.res[31:0]
-(18)ThreeTestTop.three.cpu.res[31:0]
-(19)ThreeTestTop.three.cpu.res[31:0]
-(20)ThreeTestTop.three.cpu.res[31:0]
-(21)ThreeTestTop.three.cpu.res[31:0]
-(22)ThreeTestTop.three.cpu.res[31:0]
-(23)ThreeTestTop.three.cpu.res[31:0]
-(24)ThreeTestTop.three.cpu.res[31:0]
-(25)ThreeTestTop.three.cpu.res[31:0]
-(26)ThreeTestTop.three.cpu.res[31:0]
-(27)ThreeTestTop.three.cpu.res[31:0]
-(28)ThreeTestTop.three.cpu.res[31:0]
-(29)ThreeTestTop.three.cpu.res[31:0]
-(30)ThreeTestTop.three.cpu.res[31:0]
-(31)ThreeTestTop.three.cpu.res[31:0]
-@1401201
--group_end
+WildcatTestTop.cpuTop.cpu.io_imem_stall
 @22
-ThreeTestTop.three.cpu.wbData[31:0]
-ThreeTestTop.three.cpu.wbDest[4:0]
-@28
-ThreeTestTop.three.cpu.wrEna
+WildcatTestTop.cpuTop.imem.addrReg[31:0]
+WildcatTestTop.cpuTop.imem.instructions_0[31:0]
+WildcatTestTop.cpuTop.imem.instructions_1[31:0]
+WildcatTestTop.cpuTop.imem.instructions_2[31:0]
+WildcatTestTop.cpuTop.imem.instructions_3[31:0]
+WildcatTestTop.cpuTop.imem.instructions_4[31:0]
+WildcatTestTop.cpuTop.imem.instructions_5[31:0]
 @200
 -
 -
-@22
-ThreeTestTop.three.cpu.debugRegs_8[31:0]
-ThreeTestTop.three.cpu.debugRegs_9[31:0]
-ThreeTestTop.three.cpu.debugRegs_10[31:0]
-ThreeTestTop.three.cpu.debugRegs_11[31:0]
-ThreeTestTop.three.cpu.debugRegs_12[31:0]
-ThreeTestTop.three.cpu.debugRegs_13[31:0]
-ThreeTestTop.three.cpu.debugRegs_14[31:0]
-ThreeTestTop.three.cpu.debugRegs_15[31:0]
-ThreeTestTop.three.cpu.debugRegs_16[31:0]
-ThreeTestTop.three.cpu.debugRegs_17[31:0]
-ThreeTestTop.three.cpu.debugRegs_18[31:0]
-ThreeTestTop.three.cpu.debugRegs_19[31:0]
-ThreeTestTop.three.cpu.debugRegs_20[31:0]
-ThreeTestTop.three.cpu.debugRegs_21[31:0]
-ThreeTestTop.three.cpu.debugRegs_22[31:0]
-ThreeTestTop.three.cpu.debugRegs_23[31:0]
-ThreeTestTop.three.cpu.debugRegs_24[31:0]
-ThreeTestTop.three.cpu.debugRegs_25[31:0]
-ThreeTestTop.three.cpu.debugRegs_26[31:0]
-ThreeTestTop.three.cpu.debugRegs_27[31:0]
-ThreeTestTop.three.cpu.debugRegs_28[31:0]
-ThreeTestTop.three.cpu.debugRegs_29[31:0]
-ThreeTestTop.three.cpu.debugRegs_30[31:0]
-ThreeTestTop.three.cpu.debugRegs_31[31:0]
 [pattern_trace] 1
 [pattern_trace] 0