Manually apply kevinpt#15

Author: sd2k9

hdlparse/verilog_parser.py

@@ -22,7 +22,7 @@
     'module': [
         (r'parameter\s*(signed|integer|realtime|real|time)?\s*(\[[^]]+\])?', 'parameter_start', 'parameters'),
         (
-            r'^[\(\s]*(input|inout|output)\s+(reg|supply0|supply1|tri|triand|trior|tri0|tri1|wire|wand|wor)?'
+            r'^[\(\s]*(input|inout|output)\s+(reg|supply0|supply1|tri|triand|trior|tri0|tri1|wire|wand|wor|logic)?'
             r'\s*(signed)?\s*((\[[^]]+\])+)?',
             'module_port_start', 'module_port'),
         (r'endmodule', 'end_module', '#pop'),
@@ -40,7 +40,7 @@
     ],
     'module_port': [
         (
-            r'\s*(input|inout|output)\s+(reg|supply0|supply1|tri|triand|trior|tri0|tri1|wire|wand|wor)?'
+            r'\s*(input|inout|output)\s+(reg|supply0|supply1|tri|triand|trior|tri0|tri1|wire|wand|wor|logic)?'
             r'\s*(signed)?\s*((\[[^]]+\])+)?',
             'module_port_start'),
         (r'\s*(\w+)\s*,?', 'port_param'),