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Merge pull request #67 from siliconcompiler/sc-update
split into separate importable modules
2 parents dd0e30f + 1f1691a commit c0aae8d

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README.md

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@@ -1,6 +1,6 @@
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# Lambdalib Introduction
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3-
Lambdalib is a modular hardware abstraction library decouples design from the uderlying manufacturing target. Lambdalib defines a set of generic functions that get resolved during the target technology mapping stage.
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Lambdalib is a modular hardware abstraction library decouples design from the underlying manufacturing target. Lambdalib defines a set of generic functions that get resolved during the target technology mapping stage.
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Lambdalib includes the following hardware categories:
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lambdalib/__init__.py

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@@ -1,60 +1,47 @@
1-
from siliconcompiler import Chip, Library
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from siliconcompiler import Chip
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import siliconcompiler.package as sc_package
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import glob
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import os
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import shutil
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7-
__version__ = "0.2.7"
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from lambdalib import _common
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from lambdalib import \
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auxlib, \
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fpgalib, \
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iolib, \
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padring, \
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ramlib, \
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stdlib, \
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syslib, \
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vectorlib
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9-
_libraries = (
10-
'iolib',
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'stdlib',
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'auxlib',
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'ramlib',
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'padring',
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'syslib',
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'vectorlib',
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'fpgalib'
18-
)
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__version__ = _common._version
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########################
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# SiliconCompiler Setup
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########################
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def setup(chip):
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'''Lambdalib library setup script'''
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add_idirs = ('padring',)
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libs = []
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# Iterate over all libs
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for name in _libraries:
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lib = Library(chip, f'lambdalib_{name}', package='lambdalib')
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register_data_source(lib)
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lib.add('option', 'ydir', f"lambdalib/{name}/rtl")
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if name in add_idirs:
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lib.add('option', 'idir', f"lambdalib/{name}/rtl")
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libs.append(lib)
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return libs
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def register_data_source(chip):
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sc_package.register_python_data_source(
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chip,
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"lambdalib",
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"lambdalib",
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"git+https://github.com/siliconcompiler/lambdalib.git",
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alternative_ref=f"v{__version__}",
52-
python_module_path_append="..")
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'''
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Lambdalib library setup script
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'''
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return [
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auxlib.setup(chip),
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fpgalib.setup(chip),
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iolib.setup(chip),
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padring.setup(chip),
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ramlib.setup(chip),
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stdlib.setup(chip),
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syslib.setup(chip),
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vectorlib.setup(chip)
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]
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def __get_lambdalib_dir(la_lib):
5643
path_assert = Chip('lambdalib')
57-
register_data_source(path_assert)
44+
_common.register_data_source(path_assert)
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lambdalib_path = sc_package.path(path_assert, 'lambdalib')
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return f'{lambdalib_path}/lambdalib/{la_lib}/rtl'
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lambdalib/_common.py

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import siliconcompiler.package as sc_package
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3+
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_version = "0.2.8"
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6+
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def register_data_source(chip):
8+
sc_package.register_python_data_source(
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chip,
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"lambdalib",
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"lambdalib",
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"git+https://github.com/siliconcompiler/lambdalib.git",
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alternative_ref=f"v{_version}",
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python_module_path_append="..")

lambdalib/auxlib/__init__.py

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from siliconcompiler import Library
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from lambdalib._common import register_data_source
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from lambdalib import stdlib
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5+
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########################
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# SiliconCompiler Setup
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########################
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def setup(chip):
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'''
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Lambdalib auxlib
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'''
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14+
lib = Library(chip, 'lambdalib_auxlib', package='lambdalib', auto_enable=True)
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register_data_source(lib)
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lib.add('option', 'ydir', "lambdalib/auxlib/rtl")
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lib.use(stdlib)
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return lib

lambdalib/auxlib/rtl/la_oddr.v

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@@ -17,7 +17,7 @@ module la_oddr #(
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reg in1_sh;
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always @(clk or in1) if (~clk) in1_sh <= in1;
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//Using clock as data selctor
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//Using clock as data selector
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assign out = clk ? in1_sh : in0;
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endmodule

lambdalib/fpgalib/__init__.py

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from siliconcompiler import Library
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from lambdalib._common import register_data_source
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4+
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########################
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# SiliconCompiler Setup
7+
########################
8+
def setup(chip):
9+
'''
10+
Lambdalib fpgalib
11+
'''
12+
13+
lib = Library(chip, 'lambdalib_fpgalib', package='lambdalib', auto_enable=True)
14+
register_data_source(lib)
15+
16+
lib.add('option', 'ydir', "lambdalib/fpgalib/rtl")
17+
18+
return lib

lambdalib/fpgalib/rtl/la_clb4p0.v

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*
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* 1. N=2, I=4
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* 2. test1: CLB configured as separate and4, or4 gates
28-
* 3. test2" LB confiugred as combined and7 (in[7]=ignored)
28+
* 3. test2" LB configured as combined and7 (in[7]=ignored)
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*
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******************************************************************************/
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lambdalib/iolib/README.md

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| ---------------------------------|---------|-----------------------------|
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[[la_iobidir](./rtl/la_iobidir.v) | Digital | Bidirectional
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[la_ioinput](./rtl/la_ioinput.v) | Digital | Input
9-
[la_ioxtal](./rtl/la_ioxtal.v) | Digital | Xtal tranceiver
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[la_ioxtal](./rtl/la_ioxtal.v) | Digital | Xtal transceiver
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[la_iorxdiff](./rtl/la_iorxdiff.v) | Digital | Differential input
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[la_iotxdiff](./rtl/la_iotxdiff.v) | Digital | Differential output
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[la_ioanalog](./rtl/la_ioanalog.v) | Analog | Pass through ESD protection
@@ -24,7 +24,7 @@
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## PARAMETERS
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2626
### CFGW
27-
The `CFGW` parameter defines the width of the configuration bus of the io cell. IO cells generally include a set of configuration inputs for things like drive strength and operating modes. Setting `CFGW` to a large value (eg. 16/32) should have zero impact on the design as the extra bus bits get optimized away during implementation. The connection between the generic `CFG` bus and the technology specific IO cell is done within the techology specific cell wrapper library.
27+
The `CFGW` parameter defines the width of the configuration bus of the io cell. IO cells generally include a set of configuration inputs for things like drive strength and operating modes. Setting `CFGW` to a large value (eg. 16/32) should have zero impact on the design as the extra bus bits get optimized away during implementation. The connection between the generic `CFG` bus and the technology specific IO cell is done within the technology specific cell wrapper library.
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2929
For la_bidir, the first 8 bits of the configuration bus are reserved for the functionality shown in the table below.
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lambdalib/iolib/__init__.py

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from siliconcompiler import Library
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from lambdalib._common import register_data_source
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4+
5+
########################
6+
# SiliconCompiler Setup
7+
########################
8+
def setup(chip):
9+
'''
10+
Lambdalib iolib
11+
'''
12+
13+
lib = Library(chip, 'lambdalib_iolib', package='lambdalib', auto_enable=True)
14+
register_data_source(lib)
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16+
lib.add('option', 'ydir', "lambdalib/iolib/rtl")
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return lib

lambdalib/padring/README.md

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@@ -7,7 +7,7 @@ The lamdbdalib `padring` library is an automated "pure verilog" padring generato
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## PARAMETERS
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### {NO,EA,WE,SO}NCELLS
10-
Specifies the total number of placed cells within one side of the padring, includig supply and clamp cells.
10+
Specifies the total number of placed cells within one side of the padring, including supply and clamp cells.
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1212
### {NO,EA,WE,SO}NPINS
1313
Specifies the total number of logical device pins (pads) connected to one side of the padring, not including supply pins. The `CELLMAP` parameter specifies which one of the pins should be connected to a cell.

lambdalib/padring/__init__.py

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from siliconcompiler import Library
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from lambdalib._common import register_data_source
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from lambdalib import iolib
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5+
6+
########################
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# SiliconCompiler Setup
8+
########################
9+
def setup(chip):
10+
'''
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Lambdalib padring
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'''
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14+
lib = Library(chip, 'lambdalib_padring', package='lambdalib', auto_enable=True)
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register_data_source(lib)
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17+
lib.add('option', 'idir', "lambdalib/padring/rtl")
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lib.add('option', 'ydir', "lambdalib/padring/rtl")
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lib.use(iolib)
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return lib

lambdalib/ramlib/__init__.py

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from siliconcompiler import Library
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from lambdalib._common import register_data_source
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from lambdalib import auxlib
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5+
6+
########################
7+
# SiliconCompiler Setup
8+
########################
9+
def setup(chip):
10+
'''
11+
Lambdalib ramlib
12+
'''
13+
14+
lib = Library(chip, 'lambdalib_ramlib', package='lambdalib', auto_enable=True)
15+
register_data_source(lib)
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17+
lib.add('option', 'ydir', "lambdalib/ramlib/rtl")
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19+
lib.use(auxlib)
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21+
return lib

lambdalib/ramlib/rtl/la_asyncfifo.v

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* supplied on a per macro basis.
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*
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* Technologoy specific implementations of "la_dpram" would generally include
17-
* one ore more hardcoded instantiations of RAM modules with a generate
17+
* one or more hardcoded instantiations of RAM modules with a generate
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* statement relying on the "PROP" to select between the list of modules
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* at build time.
2020
*

lambdalib/ramlib/rtl/la_dpram.v

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* supplied on a per macro basis.
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*
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* Technologoy specific implementations of "la_dpram" would generally include
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* one ore more hardcoded instantiations of RAM modules with a generate
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* one or more hardcoded instantiations of RAM modules with a generate
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* statement relying on the "PROP" to select between the list of modules
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* at build time.
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*

lambdalib/ramlib/rtl/la_spram.v

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* supplied on a per macro basis.
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*
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* Technologoy specific implementations of "la_spram" would generally include
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* one ore more hardcoded instantiations of RAM modules with a generate
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* one or more hardcoded instantiations of RAM modules with a generate
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* statement relying on the "PROP" to select between the list of modules
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* at build time.
2020
*

lambdalib/ramlib/rtl/la_spregfile.v

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* supplied on a per macro basis.
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*
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* Technologoy specific implementations of "la_spregfile" would generally
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* include one ore more hardcoded instantiations of RF modules with a generate
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* include one or more hardcoded instantiations of RF modules with a generate
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* statement relying on the "PROP" to select between the list of modules
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* at build time.
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*

lambdalib/stdlib/__init__.py

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from siliconcompiler import Library
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from lambdalib._common import register_data_source
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########################
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# SiliconCompiler Setup
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########################
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def setup(chip):
9+
'''
10+
Lambdalib stdlib
11+
'''
12+
13+
lib = Library(chip, 'lambdalib_stdlib', package='lambdalib', auto_enable=True)
14+
register_data_source(lib)
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lib.add('option', 'ydir', "lambdalib/stdlib/rtl")
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return lib

lambdalib/syslib/__init__.py

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from siliconcompiler import Library
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from lambdalib._common import register_data_source
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########################
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# SiliconCompiler Setup
7+
########################
8+
def setup(chip):
9+
'''
10+
Lambdalib syslib
11+
'''
12+
13+
lib = Library(chip, 'lambdalib_syslib', package='lambdalib', auto_enable=True)
14+
register_data_source(lib)
15+
16+
lib.add('option', 'ydir', "lambdalib/syslib/rtl")
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return lib

lambdalib/utils/templates/la_spmemory.v

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* supplied on a per macro basis.
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*
1616
* Technologoy specific implementations of "la_sp{{ type }}" would generally include
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* one ore more hardcoded instantiations of {{ type }} modules with a generate
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* one or more hardcoded instantiations of {{ type }} modules with a generate
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* statement relying on the "PROP" to select between the list of modules
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* at build time.
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*

lambdalib/vectorlib/__init__.py

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from siliconcompiler import Library
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from lambdalib._common import register_data_source
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from lambdalib import stdlib
4+
5+
6+
########################
7+
# SiliconCompiler Setup
8+
########################
9+
def setup(chip):
10+
'''
11+
Lambdalib vectorlib
12+
'''
13+
14+
lib = Library(chip, 'lambdalib_vectorlib', package='lambdalib', auto_enable=True)
15+
register_data_source(lib)
16+
17+
lib.add('option', 'ydir', "lambdalib/vectorlib/rtl")
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19+
lib.use(stdlib)
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return lib

pyproject.toml

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@@ -20,13 +20,13 @@ urls = {Homepage = "https://github.com/siliconcompiler/lambdalib"}
2020
requires-python = ">= 3.8"
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license = {file = "LICENSE"}
2222
dependencies = [
23-
"siliconcompiler >= 0.20.2",
23+
"siliconcompiler >= 0.26.0",
2424
"Jinja2 >= 3.1.3"
2525
]
2626
dynamic = ['version']
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2828
[tool.setuptools.dynamic]
29-
version = {attr = "lambdalib.__version__"}
29+
version = {attr = "lambdalib._common._version"}
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[tool.pytest.ini_options]
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testpaths = "tests"

tests/test_local_detect.py

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from siliconcompiler import Chip
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from lambdalib import register_data_source
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from lambdalib._common import register_data_source
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44

55
def test_local_install_detection():

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