sinara-hw
diff --git a/‎Bank_1.SchDoc‎
-1.95 MB b/‎Bank_1.SchDoc‎
-1.95 MB
diff --git a/‎Bank_1.Harness‎ renamed to ‎Bank_12_14_35.Harness‎ b/‎Bank_1.Harness‎ renamed to ‎Bank_12_14_35.Harness‎
diff --git a/‎Bank_12_14_35.SchDoc‎
1.95 MB b/‎Bank_12_14_35.SchDoc‎
1.95 MB
diff --git a/‎Bank_13_15.SchDoc‎
1.13 MB b/‎Bank_13_15.SchDoc‎
1.13 MB
diff --git a/‎Bank_3.Harness‎ renamed to ‎Bank_16_32_36.Harness‎ b/‎Bank_3.Harness‎ renamed to ‎Bank_16_32_36.Harness‎
diff --git a/‎Bank_16_32_36.SchDoc‎
1.84 MB b/‎Bank_16_32_36.SchDoc‎
1.84 MB
diff --git a/‎Bank_2.SchDoc‎
-1.12 MB b/‎Bank_2.SchDoc‎
-1.12 MB
diff --git a/‎Bank_3.SchDoc‎
-1.77 MB b/‎Bank_3.SchDoc‎
-1.77 MB
diff --git a/‎CLK_buffer_DRTIO_CDR.SchDoc‎
1 KB b/‎CLK_buffer_DRTIO_CDR.SchDoc‎
1 KB
diff --git a/‎ClockRecovery.Harness‎
Lines changed: 1 addition & 0 deletions b/‎ClockRecovery.Harness‎
Lines changed: 1 addition & 0 deletions
@@ -1,2 +1,3 @@
 CDR_PLL_CTRL=Main_DCXO_SDA,Main_DCXO_SCL,Main_DCXO_OE,Helper_DCXO_OE,CLK_SEL,Helper_DCXO_SDA,Helper_DCXO_SCL
 CLK_DIFF=CLK_P,CLK_N
+I2C=SDA,SCL
Original file line number	Diff line number	Diff line change
`@@ -1,2 +1,3 @@`
`1`	`1`	`CDR_PLL_CTRL=Main_DCXO_SDA,Main_DCXO_SCL,Main_DCXO_OE,Helper_DCXO_OE,CLK_SEL,Helper_DCXO_SDA,Helper_DCXO_SCL`
`2`	`2`	`CLK_DIFF=CLK_P,CLK_N`
	`3`	`+I2C=SDA,SCL`