@@ -442,22 +442,22 @@ void GPU::UpdateDMARequest()
442442 {
443443 case BlitterState::Idle:
444444 m_GPUSTAT.ready_to_send_vram = false ;
445- m_GPUSTAT.ready_to_recieve_dma = (m_fifo.IsEmpty () || m_fifo.GetSize () < m_command_total_words);
445+ m_GPUSTAT.ready_to_receive_dma = (m_fifo.IsEmpty () || m_fifo.GetSize () < m_command_total_words);
446446 break ;
447447
448448 case BlitterState::WritingVRAM:
449449 m_GPUSTAT.ready_to_send_vram = false ;
450- m_GPUSTAT.ready_to_recieve_dma = (m_fifo.GetSize () < m_fifo_size);
450+ m_GPUSTAT.ready_to_receive_dma = (m_fifo.GetSize () < m_fifo_size);
451451 break ;
452452
453453 case BlitterState::ReadingVRAM:
454454 m_GPUSTAT.ready_to_send_vram = true ;
455- m_GPUSTAT.ready_to_recieve_dma = false ;
455+ m_GPUSTAT.ready_to_receive_dma = false ;
456456 break ;
457457
458458 case BlitterState::DrawingPolyLine:
459459 m_GPUSTAT.ready_to_send_vram = false ;
460- m_GPUSTAT.ready_to_recieve_dma = (m_fifo.GetSize () < m_fifo_size);
460+ m_GPUSTAT.ready_to_receive_dma = (m_fifo.GetSize () < m_fifo_size);
461461 break ;
462462
463463 default :
@@ -473,11 +473,11 @@ void GPU::UpdateDMARequest()
473473 break ;
474474
475475 case GPUDMADirection::FIFO:
476- dma_request = m_GPUSTAT.ready_to_recieve_dma ;
476+ dma_request = m_GPUSTAT.ready_to_receive_dma ;
477477 break ;
478478
479479 case GPUDMADirection::CPUtoGP0:
480- dma_request = m_GPUSTAT.ready_to_recieve_dma ;
480+ dma_request = m_GPUSTAT.ready_to_receive_dma ;
481481 break ;
482482
483483 case GPUDMADirection::GPUREADtoCPU:
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