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Add regression test for multiple names in ANSI UDP inputs
Check that the parser accepts grouped input names, including a second input declaration in the same UDP port list. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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// Check that an ANSI UDP input declaration can contain multiple port names.
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primitive p(output o, input a, b, input c, d);
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table
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0 1 0 1 : 1;
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endtable
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endprimitive
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module test;
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wire o;
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p i_p(o, 1'b0, 1'b1, 1'b0, 1'b1);
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initial begin
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#1;
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if (o !== 1'b1) begin
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$display("FAILED: o=%b", o);
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end else begin
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$display("PASSED");
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end
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end
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endmodule

‎ivtest/regress-vvp.list‎

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timing_check_delayed_signals vvp_tests/timing_check_delayed_signals.json
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udp_ansi_initial_nonreg_fail vvp_tests/udp_ansi_initial_nonreg_fail.json
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udp_ansi_initial_reg vvp_tests/udp_ansi_initial_reg.json
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udp_ansi_input_list vvp_tests/udp_ansi_input_list.json
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udp_empty_table_fail vvp_tests/udp_empty_table_fail.json
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udp_initial_nonreg_fail vvp_tests/udp_initial_nonreg_fail.json
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udp_instance_reference_order vvp_tests/udp_instance_reference_order.json
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{
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"type" : "normal",
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"source" : "udp_ansi_input_list.v",
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"iverilog-args" : [ "-g2001" ]
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}

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