Add regression tests for inherited interface port headers

Check that bare port names inherit the interface type and modport from the
preceding port, including chained continuations. Check that unpacked
dimensions are not inherited and can be specified independently.

Also check that an inherited modport still prevents writes to input members
and that invalid initializers on interface ports remain rejected.

The positive tests encounter the existing vlog95 failures where connected
interface instances are redeclared as nets. Mark these as expected
translation failures.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

Author: larsclausen

ivtest/ivltests/sv_interface_port_inherit.v

@@ -0,0 +1,34 @@
+// Check that interface port headers are inherited across bare port names.
+
+module M(input logic a, I p, q, (* keep = 1 *) r, output wire y, z);
+
+  assign p.value = a;
+  assign q.value = !a;
+  assign r.value = p.value ^ q.value;
+  assign y = r.value;
+  assign z = q.value;
+
+endmodule
+
+interface I;
+  logic value;
+endinterface
+
+module test;
+
+  I i_p();
+  I i_q();
+  I i_r();
+  wire y, z;
+
+  M i_m(1'b1, i_p, i_q, i_r, y, z);
+
+  initial begin
+    #1;
+    if ({i_p.value, i_q.value, i_r.value, y, z} === 5'b10110)
+      $display("PASSED");
+    else
+      $display("FAILED");
+  end
+
+endmodule

ivtest/ivltests/sv_interface_port_inherit_dimensions.v

@@ -0,0 +1,36 @@
+// Check that continued interface ports use their own unpacked dimensions.
+
+interface I;
+  logic value;
+endinterface
+
+module M(I p[1:0], q, r[3:2], output wire [4:0] y);
+
+  assign y = {p[1].value, p[0].value, q.value, r[3].value, r[2].value};
+
+endmodule
+
+module test;
+
+  I i_p[1:0]();
+  I i_q();
+  I i_r[3:2]();
+  wire [4:0] y;
+
+  assign i_p[1].value = 1'b1;
+  assign i_p[0].value = 1'b0;
+  assign i_q.value = 1'b1;
+  assign i_r[3].value = 1'b0;
+  assign i_r[2].value = 1'b1;
+
+  M i_m(i_p, i_q, i_r, y);
+
+  initial begin
+    #1;
+    if (y === 5'b10101)
+      $display("PASSED");
+    else
+      $display("FAILED");
+  end
+
+endmodule

ivtest/ivltests/sv_interface_port_inherit_initializer_fail.v

@@ -0,0 +1,16 @@
+// Check that an interface port cannot acquire an initializer by continuation.
+
+interface I;
+  logic value;
+endinterface
+
+module M(I p, q = 1'b0); // Error: interface ports cannot have initializers.
+endmodule
+
+module test;
+
+  I i_p();
+  I i_q();
+  M i_m(i_p, i_q);
+
+endmodule

ivtest/ivltests/sv_interface_port_inherit_modport.v

@@ -0,0 +1,35 @@
+// Check that continued interface ports inherit the modport selector.
+
+interface I;
+  logic value;
+  modport mp(input value);
+endinterface
+
+module M(I.mp p, q, r, output wire [2:0] y);
+
+  assign y = {p.value, q.value, r.value};
+
+endmodule
+
+module test;
+
+  I i_p();
+  I i_q();
+  I i_r();
+  wire [2:0] y;
+
+  assign i_p.value = 1'b1;
+  assign i_q.value = 1'b0;
+  assign i_r.value = 1'b1;
+
+  M i_m(i_p, i_q, i_r, y);
+
+  initial begin
+    #1;
+    if (y === 3'b101)
+      $display("PASSED");
+    else
+      $display("FAILED");
+  end
+
+endmodule

ivtest/ivltests/sv_interface_port_inherit_modport_write_fail.v

@@ -0,0 +1,20 @@
+// Check that an inherited modport still prevents writes to its input members.
+
+interface I;
+  logic value;
+  modport mp(input value);
+endinterface
+
+module M(I.mp p, q);
+
+  assign q.value = 1'b1; // Error: value is an input in the inherited modport.
+
+endmodule
+
+module test;
+
+  I i_p();
+  I i_q();
+  M i_m(i_p, i_q);
+
+endmodule

ivtest/regress-vvp.list

@@ -401,28 +401,33 @@ sv_interface_identifier_interface_port_name	vvp_tests/sv_interface_identifier_in
 sv_interface_identifier_member_name	vvp_tests/sv_interface_identifier_member_name.json
 sv_interface_identifier_modport_name	vvp_tests/sv_interface_identifier_modport_name.json
 sv_interface_identifier_port_name	vvp_tests/sv_interface_identifier_port_name.json
+sv_interface_port_array_basic	vvp_tests/sv_interface_port_array_basic.json
+sv_interface_port_array_modport_restrict_fail	vvp_tests/sv_interface_port_array_modport_restrict_fail.json
+sv_interface_port_array_size_mismatch_fail	vvp_tests/sv_interface_port_array_size_mismatch_fail.json
 sv_interface_port_basic		vvp_tests/sv_interface_port_basic.json
 sv_interface_port_forward_type_after_port	vvp_tests/sv_interface_port_forward_type_after_port.json
-sv_interface_port_missing_type_fail	vvp_tests/sv_interface_port_missing_type_fail.json
-sv_interface_port_missing_modport_fail	vvp_tests/sv_interface_port_missing_modport_fail.json
-sv_interface_port_non_interface_actual_fail	vvp_tests/sv_interface_port_non_interface_actual_fail.json
-sv_interface_port_wrong_type_fail	vvp_tests/sv_interface_port_wrong_type_fail.json
-sv_interface_port_modport_input_write_fail	vvp_tests/sv_interface_port_modport_input_write_fail.json
-sv_interface_port_unlisted_member_fail	vvp_tests/sv_interface_port_unlisted_member_fail.json
-sv_interface_port_unmodported_basic	vvp_tests/sv_interface_port_unmodported_basic.json
-sv_interface_port_unmodported_missing_type_fail	vvp_tests/sv_interface_port_unmodported_missing_type_fail.json
 sv_interface_port_forwarding	vvp_tests/sv_interface_port_forwarding.json
 sv_interface_port_forwarding_restrict_fail	vvp_tests/sv_interface_port_forwarding_restrict_fail.json
-sv_interface_port_positional	vvp_tests/sv_interface_port_positional.json
-sv_interface_port_positional_unconnected_fail	vvp_tests/sv_interface_port_positional_unconnected_fail.json
-sv_interface_port_wildcard	vvp_tests/sv_interface_port_wildcard.json
 sv_interface_port_indexed_actual	vvp_tests/sv_interface_port_indexed_actual.json
 sv_interface_port_indexed_actual_generate	vvp_tests/sv_interface_port_indexed_actual_generate.json
-sv_interface_port_array_basic	vvp_tests/sv_interface_port_array_basic.json
-sv_interface_port_array_modport_restrict_fail	vvp_tests/sv_interface_port_array_modport_restrict_fail.json
-sv_interface_port_array_size_mismatch_fail	vvp_tests/sv_interface_port_array_size_mismatch_fail.json
+sv_interface_port_inherit	vvp_tests/sv_interface_port_inherit.json
+sv_interface_port_inherit_dimensions	vvp_tests/sv_interface_port_inherit_dimensions.json
+sv_interface_port_inherit_initializer_fail	vvp_tests/sv_interface_port_inherit_initializer_fail.json
+sv_interface_port_inherit_modport	vvp_tests/sv_interface_port_inherit_modport.json
+sv_interface_port_inherit_modport_write_fail	vvp_tests/sv_interface_port_inherit_modport_write_fail.json
+sv_interface_port_missing_modport_fail	vvp_tests/sv_interface_port_missing_modport_fail.json
+sv_interface_port_missing_type_fail	vvp_tests/sv_interface_port_missing_type_fail.json
+sv_interface_port_modport_input_write_fail	vvp_tests/sv_interface_port_modport_input_write_fail.json
+sv_interface_port_non_interface_actual_fail	vvp_tests/sv_interface_port_non_interface_actual_fail.json
 sv_interface_port_plain_ansi_regression	vvp_tests/sv_interface_port_plain_ansi_regression.json
+sv_interface_port_positional	vvp_tests/sv_interface_port_positional.json
+sv_interface_port_positional_unconnected_fail	vvp_tests/sv_interface_port_positional_unconnected_fail.json
 sv_interface_port_typedef_ansi_regression	vvp_tests/sv_interface_port_typedef_ansi_regression.json
+sv_interface_port_unlisted_member_fail	vvp_tests/sv_interface_port_unlisted_member_fail.json
+sv_interface_port_unmodported_basic	vvp_tests/sv_interface_port_unmodported_basic.json
+sv_interface_port_unmodported_missing_type_fail	vvp_tests/sv_interface_port_unmodported_missing_type_fail.json
+sv_interface_port_wildcard	vvp_tests/sv_interface_port_wildcard.json
+sv_interface_port_wrong_type_fail	vvp_tests/sv_interface_port_wrong_type_fail.json
 sv_literals			vvp_tests/sv_literals.json
 sv_lval_concat_class_fail1	vvp_tests/sv_lval_concat_class_fail1.json
 sv_lval_concat_class_fail2	vvp_tests/sv_lval_concat_class_fail2.json

ivtest/vvp_tests/sv_interface_port_inherit.json

@@ -0,0 +1,9 @@
+{
+    "type"          : "normal",
+    "source"        : "sv_interface_port_inherit.v",
+    "iverilog-args" : [ "-g2005-sv" ],
+    "vlog95" : {
+        "__comment"     : "vlog95 redeclares connected interface instances as nets",
+        "type"          : "TE"
+    }
+}

ivtest/vvp_tests/sv_interface_port_inherit_dimensions.json

@@ -0,0 +1,9 @@
+{
+    "type"          : "normal",
+    "source"        : "sv_interface_port_inherit_dimensions.v",
+    "iverilog-args" : [ "-g2005-sv" ],
+    "vlog95" : {
+        "__comment"     : "vlog95 redeclares connected interface instances as nets",
+        "type"          : "TE"
+    }
+}

ivtest/vvp_tests/sv_interface_port_inherit_initializer_fail.json

@@ -0,0 +1,5 @@
+{
+    "type"          : "CE",
+    "source"        : "sv_interface_port_inherit_initializer_fail.v",
+    "iverilog-args" : [ "-g2005-sv" ]
+}

ivtest/vvp_tests/sv_interface_port_inherit_modport.json

@@ -0,0 +1,9 @@
+{
+    "type"          : "normal",
+    "source"        : "sv_interface_port_inherit_modport.v",
+    "iverilog-args" : [ "-g2005-sv" ],
+    "vlog95" : {
+        "__comment"     : "vlog95 redeclares connected interface instances as nets",
+        "type"          : "TE"
+    }
+}