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Add regression test for an interface name matching a typedef
Check that a forward interface name used in a port declaration can have the same spelling as a visible `typedef`. Access a member through the port to make sure it is interpreted as an interface rather than a named data type. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
1 parent 984e757 commit a079347

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// Check that a forward interface name can match a visible typedef at a port.
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package p;
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typedef int IFACE;
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endpackage
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import p::*;
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module dut(IFACE i_iface, output logic result);
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assign result = i_iface.value;
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endmodule
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interface IFACE;
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logic value;
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endinterface
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module test;
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IFACE i_iface();
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logic result;
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dut i_dut(i_iface, result);
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initial begin
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i_iface.value = 1'b1;
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#1;
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if (result === 1'b1) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule

‎ivtest/regress-vvp.list‎

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sv_type_identifier_implicit_port_fail vvp_tests/sv_type_identifier_implicit_port_fail.json
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sv_type_identifier_inherited_property_shadow vvp_tests/sv_type_identifier_inherited_property_shadow.json
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sv_type_identifier_interface_forward_instance vvp_tests/sv_type_identifier_interface_forward_instance.json
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sv_type_identifier_interface_forward_port vvp_tests/sv_type_identifier_interface_forward_port.json
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sv_type_identifier_modport_name vvp_tests/sv_type_identifier_modport_name.json
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sv_type_identifier_modport_named_port vvp_tests/sv_type_identifier_modport_named_port.json
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sv_type_identifier_module_forward_instance vvp_tests/sv_type_identifier_module_forward_instance.json
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{
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"type" : "normal",
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"source" : "sv_type_identifier_interface_forward_port.v",
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"iverilog-args" : [ "-g2005-sv" ],
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"vlog95" : {
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"__comment" : "Interfaces are not supported",
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"type" : "TE"
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}
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}

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