@@ -2085,7 +2085,7 @@ void PGModule::elaborate_mod_(Design*des, const Module*rmod, NetScope*scope) con
20852085 // We do not support automatic bits to real conversion
20862086 // for inout ports.
20872087 if ((sig->data_type () == IVL_VT_REAL ) &&
2088- !prts. empty () && (prts[0 ]->data_type () != IVL_VT_REAL )) {
2088+ (prts[0 ]->data_type () != IVL_VT_REAL )) {
20892089 cerr << pins[idx]->get_fileline () << " : error: "
20902090 << " Cannot automatically connect bit based "
20912091 " inout port " << (idx+1 ) << " (" << port_name
@@ -2096,7 +2096,7 @@ void PGModule::elaborate_mod_(Design*des, const Module*rmod, NetScope*scope) con
20962096 }
20972097
20982098 // We do not support real inout ports at all.
2099- if (! prts. empty () && (prts [0 ]->data_type () == IVL_VT_REAL ) ) {
2099+ if (prts[0 ]->data_type () == IVL_VT_REAL ) {
21002100 cerr << pins[idx]->get_fileline () << " : error: "
21012101 << " No support for connecting real inout ports ("
21022102 " port " << (idx+1 ) << " (" << port_name
@@ -2150,7 +2150,7 @@ void PGModule::elaborate_mod_(Design*des, const Module*rmod, NetScope*scope) con
21502150 // width cast. Since a real is only one bit the whole
21512151 // thing needs to go to each instance when arrayed.
21522152 if ((sig->data_type () != IVL_VT_REAL ) &&
2153- !prts. empty () && (prts[0 ]->data_type () == IVL_VT_REAL )) {
2153+ (prts[0 ]->data_type () == IVL_VT_REAL )) {
21542154 if (sig->vector_width () % instance.size () != 0 ) {
21552155 cerr << pins[idx]->get_fileline () << " : error: "
21562156 " When automatically converting a real "
@@ -2175,7 +2175,7 @@ void PGModule::elaborate_mod_(Design*des, const Module*rmod, NetScope*scope) con
21752175 // If we have a bit/vector port driving a single real
21762176 // signal then we convert the value to a real.
21772177 if ((sig->data_type () == IVL_VT_REAL ) &&
2178- !prts. empty () && (prts[0 ]->data_type () != IVL_VT_REAL )) {
2178+ (prts[0 ]->data_type () != IVL_VT_REAL )) {
21792179 prts_vector_width -= prts[0 ]->vector_width () - 1 ;
21802180 prts[0 ] = cast_to_real (des, scope, prts[0 ]);
21812181 // No support for multiple real drivers.
@@ -2193,7 +2193,7 @@ void PGModule::elaborate_mod_(Design*des, const Module*rmod, NetScope*scope) con
21932193 // If we have a 4-state bit/vector port driving a
21942194 // 2-state signal then we convert the value to 2-state.
21952195 if ((sig->data_type () == IVL_VT_BOOL ) &&
2196- !prts. empty () && (prts[0 ]->data_type () == IVL_VT_LOGIC )) {
2196+ (prts[0 ]->data_type () == IVL_VT_LOGIC )) {
21972197 for (unsigned pidx = 0 ; pidx < prts.size (); pidx += 1 ) {
21982198 prts[pidx] = cast_to_int2 (des, scope, prts[pidx],
21992199 prts[pidx]->vector_width ());
@@ -2203,7 +2203,7 @@ void PGModule::elaborate_mod_(Design*des, const Module*rmod, NetScope*scope) con
22032203 // A real to real connection is not allowed for arrayed
22042204 // instances. You cannot have multiple real drivers.
22052205 if ((sig->data_type () == IVL_VT_REAL ) &&
2206- !prts. empty () && (prts[0 ]->data_type () == IVL_VT_REAL ) &&
2206+ (prts[0 ]->data_type () == IVL_VT_REAL ) &&
22072207 instance.size () != 1 ) {
22082208 cerr << pins[idx]->get_fileline () << " : error: "
22092209 << " An arrayed instance of " << rmod->mod_name ()
@@ -4689,6 +4689,11 @@ NetProc* PCallTask::elaborate_build_call_(Design*des, NetScope*scope,
46894689 << peek_tail_name (path_) << " ' is not allowed." << endl;
46904690 des->errors ++;
46914691 }
4692+ } else {
4693+ cerr << get_fileline () << " : error: trying to generate a call to '"
4694+ << peek_tail_name (path_) << " ' which is not a task of function." << endl;
4695+ des->errors ++;
4696+ return nullptr ;
46924697 }
46934698
46944699 /* The caller has checked the parms_ size to make sure it
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