$bits() must be given a valid data type

Author: caryr

compiler.h

@@ -229,6 +229,9 @@ extern bool gn_strict_parameter_declaration;
  */
 extern bool gn_strict_net_var_declaration;
 
+/* Allow $bits() to take a real argument. Not allowed by default. */
+extern bool gn_allow_real_arg_to_bits;
+
 static inline bool gn_system_verilog(void)
 {
       if (generation_flag >= GN_VER2005_SV)

driver/iverilog.man.in

@@ -1,4 +1,4 @@
-.TH iverilog 1 "Jan 13th, 2026" "" "Version @VERSION@"
+.TH iverilog 1 "Sep 4th, 2026" "" "Version @VERSION@"
 .SH NAME
 iverilog - Icarus Verilog compiler
 
@@ -205,6 +205,12 @@ extensions. This includes the binary bitwise NAND and NOR operators
 and allowing the binary arithmetic modulus operator to operate on real
 operands.
 .TP 8
+.B -gallow-real-arg-to-bits\fI|\fP-gno-allow-real-arg-to-bits
+Starting in 1800-2012 the standard forbids passing a real value
+to \fB$bits()\fP. The compiler has traditionally reported the width
+of a real as 1. This is now flagged as an error by default. You can
+use this flag to enable the previous functionality.
+.TP 8
 .B -I\fIincludedir\fP
 Append directory \fIincludedir\fP to list of directories searched
 for Verilog include files. The \fB\-I\fP switch may be used many times

driver/main.c

@@ -138,6 +138,7 @@ const char*gen_io_range_error = "io-range-error";
 const char*gen_strict_ca_eval = "no-strict-ca-eval";
 const char*gen_strict_expr_width = "no-strict-expr-width";
 const char*gen_shared_loop_index = "shared-loop-index";
+const char*gen_allow_real_arg_to_bits = "no-allow-real-arg-to-bits";
 const char*gen_verilog_ams = "no-verilog-ams";
 const char*gen_strict_net_var_declaration = "strict-net-var-declaration";
 const char*gen_strict_parameter_declaration = "strict-parameter-declaration";
@@ -832,6 +833,12 @@ static int process_generation(const char*name)
       else if (strcmp(name,"no-shared-loop-index") == 0)
 	    gen_shared_loop_index = "no-shared-loop-index";
 
+      else if (strcmp(name,"allow-real-arg-to-bits") == 0)
+            gen_allow_real_arg_to_bits = "allow-real-arg-to-bits";
+
+      else if (strcmp(name,"no-allow-real-arg-to-bits") == 0)
+            gen_allow_real_arg_to_bits = "no-allow-real-arg-to-bits";
+
       else if (strcmp(name,"verilog-ams") == 0)
 	    gen_verilog_ams = "verilog-ams";
 
@@ -1445,6 +1452,7 @@ int main(int argc, char **argv)
       fprintf(iconfig_file, "generation:%s\n", gen_strict_ca_eval);
       fprintf(iconfig_file, "generation:%s\n", gen_strict_expr_width);
       fprintf(iconfig_file, "generation:%s\n", gen_shared_loop_index);
+      fprintf(iconfig_file, "generation:%s\n", gen_allow_real_arg_to_bits);
       fprintf(iconfig_file, "generation:%s\n", gen_verilog_ams);
       fprintf(iconfig_file, "generation:%s\n", gen_strict_net_var_declaration);
       fprintf(iconfig_file, "generation:%s\n", gen_strict_parameter_declaration);

elab_expr.cc

@@ -2357,7 +2357,7 @@ NetExpr* PECallFunction::elaborate_sfunc_(Design*des, NetScope*scope,
 		  if (!data_type->packed()) {
 			use_width = 0;
 			cerr << get_fileline() << ": error: "
-			     << "Invalid data type for $bits()."
+			     << "Invalid data type for " << name << "()."
 			     << endl;
 			des->errors++;
 		  } else {
@@ -2369,6 +2369,31 @@ NetExpr* PECallFunction::elaborate_sfunc_(Design*des, NetScope*scope,
 		  }
 
 	    } else {
+		  switch(expr->expr_type()) {
+		    case IVL_VT_BOOL:
+		    case IVL_VT_LOGIC: // This also covers IVL_VT_VECTOR
+		    case IVL_VT_STRING:
+			break;
+		    case IVL_VT_NO_TYPE:
+			cerr << get_fileline() << ": error: Argument with no known data type '"
+			     << *expr << "' passed to " << name << "()." << endl;
+			des->errors++;
+			break;
+		    case IVL_VT_REAL:
+			  // Traditionally iverilog returned 1 for the width of a real.
+			  // Since 1800-2012 this is now forbidden by the standard.
+			  // To support older code skip the error when requested.
+			if (gn_allow_real_arg_to_bits) break;
+			cerr << get_fileline() << ": error: Real argument '"
+			     << *expr << "' passed to " << name << "()." << endl;
+			des->errors++;
+			break;
+		    default:
+			cerr << get_fileline() << ": sorry: Argument '" << *expr << "' of type '"
+			     << expr->expr_type() << "' passed to " << name << "(). is not "
+			        "currently supported" << endl;
+			des->errors++;
+		  }
 		  use_width = expr->expr_width();
 		  if (debug_elaborate) {
 			cerr << get_fileline() << ": PECallFunction::elaborate_sfunc_: "

ivtest/gold/br_gh1112a.gold

@@ -0,0 +1,2 @@
+./ivltests/br_gh1112a.v:3: error: Argument with no known data type 'value' passed to $bits().
+1 error(s) during elaboration.

ivtest/gold/br_gh1112b.gold

@@ -0,0 +1,2 @@
+./ivltests/br_gh1112b.v:3: error: Argument with no known data type 'top' passed to $bits().
+1 error(s) during elaboration.

ivtest/gold/br_gh1112c.gold

@@ -0,0 +1,2 @@
+./ivltests/br_gh1112c.v:3: error: Real argument '1.00000' passed to $bits().
+1 error(s) during elaboration.

ivtest/gold/early_sig_elab3-iverilog-stderr.gold

@@ -1,2 +1,3 @@
 ivltests/early_sig_elab3.v:8: error: Circular dependency detected in declaration of 'a'.
-1 error(s) during elaboration.
+ivltests/early_sig_elab3.v:9: error: Argument with no known data type 'test.a' passed to $bits().
+2 error(s) during elaboration.

ivtest/ivltests/br_gh1112a.v

@@ -0,0 +1,5 @@
+module top;
+  // An undefined value cannot be passed to $bits().
+  localparam width = $bits(value);
+  initial $display("FAILED: elaborated a width of %0d", width);
+endmodule

ivtest/ivltests/br_gh1112b.v

@@ -0,0 +1,5 @@
+module top;
+  // A scope cannot be passed to $bits().
+  localparam width = $bits(top);
+  initial $display("FAILED: elaborated a width of %0d", width);
+endmodule