diff --git a/README.md b/README.md
index 6eed49393d..f258a6f633 100644
--- a/README.md
+++ b/README.md
@@ -156,6 +156,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
 
 | Status | Device(s) | Name | Release | Notes |
 | :----: | :-------: | ---- | :-----: | :---- |
+| :yellow_heart: | STM32C011F6 | [STM32C0116-DK](https://www.st.com/en/evaluation-tools/stm32c0116-dk.html) | **2.6.0** |  |
 | :green_heart: | STM32C031C6 | [STM32C0316-DK](https://www.st.com/en/evaluation-tools/stm32c0316-dk.html) | *2.5.0* |  |
 | :green_heart:  | STM32F030R8 | [32F0308DISCOVERY](http://www.st.com/en/evaluation-tools/32f0308discovery.html) | *1.3.0* |  |
 | :green_heart:  | STM32F072RB | [32F072BDISCOVERY](https://www.st.com/en/evaluation-tools/32f072bdiscovery.html) | *1.5.0* |  |
diff --git a/boards.txt b/boards.txt
index 575990b107..15fec736e6 100644
--- a/boards.txt
+++ b/boards.txt
@@ -929,6 +929,19 @@ Disco.menu.pnum.B_U585I_IOT02A.build.variant=STM32U5xx/U575A(G-I)IxQ_U585AIIxQ
 Disco.menu.pnum.B_U585I_IOT02A.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS
 Disco.menu.pnum.B_U585I_IOT02A.build.cmsis_lib_gcc=arm_ARMv8MMLlfsp_math
 
+# STM32C0316-DK board
+Disco.menu.pnum.STM32C0116_DK=STM32C0116-DK
+Disco.menu.pnum.STM32C0116_DK.node="No_mass_storage_for_this_board_Use_STLink_upload_method"
+Disco.menu.pnum.STM32C0116_DK.upload.maximum_size=32768
+Disco.menu.pnum.STM32C0116_DK.upload.maximum_data_size=6144
+Disco.menu.pnum.STM32C0116_DK.build.mcu=cortex-m0plus
+Disco.menu.pnum.STM32C0116_DK.build.board=STM32C0116_DK
+Disco.menu.pnum.STM32C0116_DK.build.series=STM32C0xx
+Disco.menu.pnum.STM32C0116_DK.build.product_line=STM32C011xx
+Disco.menu.pnum.STM32C0116_DK.build.variant=STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P
+Disco.menu.pnum.STM32C0116_DK.build.cmsis_lib_gcc=arm_cortexM0l_math
+Disco.menu.pnum.STM32C0116_DK.build.st_extra_flags=-D{build.product_line} {build.xSerial} -D__CORTEX_SC=0
+
 # STM32C0316-DK board
 Disco.menu.pnum.STM32C0316_DK=STM32C0316-DK
 Disco.menu.pnum.STM32C0316_DK.node="No_mass_storage_for_this_board_Use_STLink_upload_method"
diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake
index 6f239c0c9e..379d245ff2 100644
--- a/cmake/boards_db.cmake
+++ b/cmake/boards_db.cmake
@@ -6538,6 +6538,291 @@ target_compile_options(FYSETC_S6_xusb_HSFS INTERFACE
   "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
 )
 
+# GENERIC_C011D6YX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_C011D6YX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P")
+set(GENERIC_C011D6YX_MAXSIZE 32768)
+set(GENERIC_C011D6YX_MAXDATASIZE 6144)
+set(GENERIC_C011D6YX_MCU cortex-m0plus)
+set(GENERIC_C011D6YX_FPCONF "-")
+add_library(GENERIC_C011D6YX INTERFACE)
+target_compile_options(GENERIC_C011D6YX INTERFACE
+  "SHELL:-DSTM32C011xx  -D__CORTEX_SC=0"
+  "SHELL:"
+  "SHELL:"
+  "SHELL: "
+  -mcpu=${GENERIC_C011D6YX_MCU}
+)
+target_compile_definitions(GENERIC_C011D6YX INTERFACE
+  "STM32C0xx"
+	"ARDUINO_GENERIC_C011D6YX"
+	"BOARD_NAME=\"GENERIC_C011D6YX\""
+	"BOARD_ID=GENERIC_C011D6YX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_C011D6YX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/
+  ${GENERIC_C011D6YX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_C011D6YX INTERFACE
+  "LINKER:--default-script=${GENERIC_C011D6YX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=32768"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=6144"
+  "SHELL: "
+  -mcpu=${GENERIC_C011D6YX_MCU}
+)
+target_link_libraries(GENERIC_C011D6YX INTERFACE
+  arm_cortexM0l_math
+)
+
+add_library(GENERIC_C011D6YX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_C011D6YX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_C011D6YX_serial_generic INTERFACE)
+target_compile_options(GENERIC_C011D6YX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_C011D6YX_serial_none INTERFACE)
+target_compile_options(GENERIC_C011D6YX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+
+# GENERIC_C011F4PX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_C011F4PX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P")
+set(GENERIC_C011F4PX_MAXSIZE 16384)
+set(GENERIC_C011F4PX_MAXDATASIZE 6144)
+set(GENERIC_C011F4PX_MCU cortex-m0plus)
+set(GENERIC_C011F4PX_FPCONF "-")
+add_library(GENERIC_C011F4PX INTERFACE)
+target_compile_options(GENERIC_C011F4PX INTERFACE
+  "SHELL:-DSTM32C011xx  -D__CORTEX_SC=0"
+  "SHELL:"
+  "SHELL:"
+  "SHELL: "
+  -mcpu=${GENERIC_C011F4PX_MCU}
+)
+target_compile_definitions(GENERIC_C011F4PX INTERFACE
+  "STM32C0xx"
+	"ARDUINO_GENERIC_C011F4PX"
+	"BOARD_NAME=\"GENERIC_C011F4PX\""
+	"BOARD_ID=GENERIC_C011F4PX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_C011F4PX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/
+  ${GENERIC_C011F4PX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_C011F4PX INTERFACE
+  "LINKER:--default-script=${GENERIC_C011F4PX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=16384"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=6144"
+  "SHELL: "
+  -mcpu=${GENERIC_C011F4PX_MCU}
+)
+target_link_libraries(GENERIC_C011F4PX INTERFACE
+  arm_cortexM0l_math
+)
+
+add_library(GENERIC_C011F4PX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_C011F4PX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_C011F4PX_serial_generic INTERFACE)
+target_compile_options(GENERIC_C011F4PX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_C011F4PX_serial_none INTERFACE)
+target_compile_options(GENERIC_C011F4PX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+
+# GENERIC_C011F4UX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_C011F4UX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P")
+set(GENERIC_C011F4UX_MAXSIZE 16384)
+set(GENERIC_C011F4UX_MAXDATASIZE 6144)
+set(GENERIC_C011F4UX_MCU cortex-m0plus)
+set(GENERIC_C011F4UX_FPCONF "-")
+add_library(GENERIC_C011F4UX INTERFACE)
+target_compile_options(GENERIC_C011F4UX INTERFACE
+  "SHELL:-DSTM32C011xx  -D__CORTEX_SC=0"
+  "SHELL:"
+  "SHELL:"
+  "SHELL: "
+  -mcpu=${GENERIC_C011F4UX_MCU}
+)
+target_compile_definitions(GENERIC_C011F4UX INTERFACE
+  "STM32C0xx"
+	"ARDUINO_GENERIC_C011F4UX"
+	"BOARD_NAME=\"GENERIC_C011F4UX\""
+	"BOARD_ID=GENERIC_C011F4UX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_C011F4UX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/
+  ${GENERIC_C011F4UX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_C011F4UX INTERFACE
+  "LINKER:--default-script=${GENERIC_C011F4UX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=16384"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=6144"
+  "SHELL: "
+  -mcpu=${GENERIC_C011F4UX_MCU}
+)
+target_link_libraries(GENERIC_C011F4UX INTERFACE
+  arm_cortexM0l_math
+)
+
+add_library(GENERIC_C011F4UX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_C011F4UX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_C011F4UX_serial_generic INTERFACE)
+target_compile_options(GENERIC_C011F4UX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_C011F4UX_serial_none INTERFACE)
+target_compile_options(GENERIC_C011F4UX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+
+# GENERIC_C011F6PX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_C011F6PX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P")
+set(GENERIC_C011F6PX_MAXSIZE 32768)
+set(GENERIC_C011F6PX_MAXDATASIZE 6144)
+set(GENERIC_C011F6PX_MCU cortex-m0plus)
+set(GENERIC_C011F6PX_FPCONF "-")
+add_library(GENERIC_C011F6PX INTERFACE)
+target_compile_options(GENERIC_C011F6PX INTERFACE
+  "SHELL:-DSTM32C011xx  -D__CORTEX_SC=0"
+  "SHELL:"
+  "SHELL:"
+  "SHELL: "
+  -mcpu=${GENERIC_C011F6PX_MCU}
+)
+target_compile_definitions(GENERIC_C011F6PX INTERFACE
+  "STM32C0xx"
+	"ARDUINO_GENERIC_C011F6PX"
+	"BOARD_NAME=\"GENERIC_C011F6PX\""
+	"BOARD_ID=GENERIC_C011F6PX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_C011F6PX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/
+  ${GENERIC_C011F6PX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_C011F6PX INTERFACE
+  "LINKER:--default-script=${GENERIC_C011F6PX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=32768"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=6144"
+  "SHELL: "
+  -mcpu=${GENERIC_C011F6PX_MCU}
+)
+target_link_libraries(GENERIC_C011F6PX INTERFACE
+  arm_cortexM0l_math
+)
+
+add_library(GENERIC_C011F6PX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_C011F6PX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_C011F6PX_serial_generic INTERFACE)
+target_compile_options(GENERIC_C011F6PX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_C011F6PX_serial_none INTERFACE)
+target_compile_options(GENERIC_C011F6PX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+
+# GENERIC_C011F6UX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_C011F6UX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P")
+set(GENERIC_C011F6UX_MAXSIZE 32768)
+set(GENERIC_C011F6UX_MAXDATASIZE 6144)
+set(GENERIC_C011F6UX_MCU cortex-m0plus)
+set(GENERIC_C011F6UX_FPCONF "-")
+add_library(GENERIC_C011F6UX INTERFACE)
+target_compile_options(GENERIC_C011F6UX INTERFACE
+  "SHELL:-DSTM32C011xx  -D__CORTEX_SC=0"
+  "SHELL:"
+  "SHELL:"
+  "SHELL: "
+  -mcpu=${GENERIC_C011F6UX_MCU}
+)
+target_compile_definitions(GENERIC_C011F6UX INTERFACE
+  "STM32C0xx"
+	"ARDUINO_GENERIC_C011F6UX"
+	"BOARD_NAME=\"GENERIC_C011F6UX\""
+	"BOARD_ID=GENERIC_C011F6UX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_C011F6UX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/
+  ${GENERIC_C011F6UX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_C011F6UX INTERFACE
+  "LINKER:--default-script=${GENERIC_C011F6UX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=32768"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=6144"
+  "SHELL: "
+  -mcpu=${GENERIC_C011F6UX_MCU}
+)
+target_link_libraries(GENERIC_C011F6UX INTERFACE
+  arm_cortexM0l_math
+)
+
+add_library(GENERIC_C011F6UX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_C011F6UX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_C011F6UX_serial_generic INTERFACE)
+target_compile_options(GENERIC_C011F6UX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_C011F6UX_serial_none INTERFACE)
+target_compile_options(GENERIC_C011F6UX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+
 # GENERIC_C031C4TX
 # -----------------------------------------------------------------------------
 
@@ -6766,6 +7051,120 @@ target_compile_options(GENERIC_C031C6UX_serial_none INTERFACE
   "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
 )
 
+# GENERIC_C031F4PX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_C031F4PX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P")
+set(GENERIC_C031F4PX_MAXSIZE 16384)
+set(GENERIC_C031F4PX_MAXDATASIZE 12288)
+set(GENERIC_C031F4PX_MCU cortex-m0plus)
+set(GENERIC_C031F4PX_FPCONF "-")
+add_library(GENERIC_C031F4PX INTERFACE)
+target_compile_options(GENERIC_C031F4PX INTERFACE
+  "SHELL:-DSTM32C031xx  -D__CORTEX_SC=0"
+  "SHELL:"
+  "SHELL:"
+  "SHELL: "
+  -mcpu=${GENERIC_C031F4PX_MCU}
+)
+target_compile_definitions(GENERIC_C031F4PX INTERFACE
+  "STM32C0xx"
+	"ARDUINO_GENERIC_C031F4PX"
+	"BOARD_NAME=\"GENERIC_C031F4PX\""
+	"BOARD_ID=GENERIC_C031F4PX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_C031F4PX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/
+  ${GENERIC_C031F4PX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_C031F4PX INTERFACE
+  "LINKER:--default-script=${GENERIC_C031F4PX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=16384"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=12288"
+  "SHELL: "
+  -mcpu=${GENERIC_C031F4PX_MCU}
+)
+target_link_libraries(GENERIC_C031F4PX INTERFACE
+  arm_cortexM0l_math
+)
+
+add_library(GENERIC_C031F4PX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_C031F4PX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_C031F4PX_serial_generic INTERFACE)
+target_compile_options(GENERIC_C031F4PX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_C031F4PX_serial_none INTERFACE)
+target_compile_options(GENERIC_C031F4PX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+
+# GENERIC_C031F6PX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_C031F6PX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P")
+set(GENERIC_C031F6PX_MAXSIZE 32768)
+set(GENERIC_C031F6PX_MAXDATASIZE 12288)
+set(GENERIC_C031F6PX_MCU cortex-m0plus)
+set(GENERIC_C031F6PX_FPCONF "-")
+add_library(GENERIC_C031F6PX INTERFACE)
+target_compile_options(GENERIC_C031F6PX INTERFACE
+  "SHELL:-DSTM32C031xx  -D__CORTEX_SC=0"
+  "SHELL:"
+  "SHELL:"
+  "SHELL: "
+  -mcpu=${GENERIC_C031F6PX_MCU}
+)
+target_compile_definitions(GENERIC_C031F6PX INTERFACE
+  "STM32C0xx"
+	"ARDUINO_GENERIC_C031F6PX"
+	"BOARD_NAME=\"GENERIC_C031F6PX\""
+	"BOARD_ID=GENERIC_C031F6PX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_C031F6PX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/
+  ${GENERIC_C031F6PX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_C031F6PX INTERFACE
+  "LINKER:--default-script=${GENERIC_C031F6PX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=32768"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=12288"
+  "SHELL: "
+  -mcpu=${GENERIC_C031F6PX_MCU}
+)
+target_link_libraries(GENERIC_C031F6PX INTERFACE
+  arm_cortexM0l_math
+)
+
+add_library(GENERIC_C031F6PX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_C031F6PX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_C031F6PX_serial_generic INTERFACE)
+target_compile_options(GENERIC_C031F6PX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_C031F6PX_serial_none INTERFACE)
+target_compile_options(GENERIC_C031F6PX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+
 # GENERIC_F030C6TX
 # -----------------------------------------------------------------------------
 
@@ -48348,7 +48747,7 @@ target_link_libraries(GENERIC_F446VETX_hid INTERFACE
 
 set(GENERIC_F722RCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F7xx/F722R(C-E)T_F730R8T_F732RET")
 set(GENERIC_F722RCTX_MAXSIZE 262144)
-set(GENERIC_F722RCTX_MAXDATASIZE 196608)
+set(GENERIC_F722RCTX_MAXDATASIZE 262144)
 set(GENERIC_F722RCTX_MCU cortex-m7)
 set(GENERIC_F722RCTX_FPCONF "-")
 add_library(GENERIC_F722RCTX INTERFACE)
@@ -48379,7 +48778,7 @@ target_link_options(GENERIC_F722RCTX INTERFACE
   "LINKER:--default-script=${GENERIC_F722RCTX_VARIANT_PATH}/ldscript.ld"
   "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
 	"LINKER:--defsym=LD_MAX_SIZE=262144"
-	"LINKER:--defsym=LD_MAX_DATA_SIZE=196608"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=262144"
   "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
   -mcpu=${GENERIC_F722RCTX_MCU}
 )
@@ -48433,7 +48832,7 @@ target_compile_options(GENERIC_F722RCTX_xusb_HSFS INTERFACE
 
 set(GENERIC_F722RETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F7xx/F722R(C-E)T_F730R8T_F732RET")
 set(GENERIC_F722RETX_MAXSIZE 524288)
-set(GENERIC_F722RETX_MAXDATASIZE 196608)
+set(GENERIC_F722RETX_MAXDATASIZE 262144)
 set(GENERIC_F722RETX_MCU cortex-m7)
 set(GENERIC_F722RETX_FPCONF "-")
 add_library(GENERIC_F722RETX INTERFACE)
@@ -48464,7 +48863,7 @@ target_link_options(GENERIC_F722RETX INTERFACE
   "LINKER:--default-script=${GENERIC_F722RETX_VARIANT_PATH}/ldscript.ld"
   "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
 	"LINKER:--defsym=LD_MAX_SIZE=524288"
-	"LINKER:--defsym=LD_MAX_DATA_SIZE=196608"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=262144"
   "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
   -mcpu=${GENERIC_F722RETX_MCU}
 )
@@ -48518,7 +48917,7 @@ target_compile_options(GENERIC_F722RETX_xusb_HSFS INTERFACE
 
 set(GENERIC_F722ZCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F7xx/F722Z(C-E)T_F732ZET")
 set(GENERIC_F722ZCTX_MAXSIZE 262144)
-set(GENERIC_F722ZCTX_MAXDATASIZE 196608)
+set(GENERIC_F722ZCTX_MAXDATASIZE 262144)
 set(GENERIC_F722ZCTX_MCU cortex-m7)
 set(GENERIC_F722ZCTX_FPCONF "-")
 add_library(GENERIC_F722ZCTX INTERFACE)
@@ -48549,7 +48948,7 @@ target_link_options(GENERIC_F722ZCTX INTERFACE
   "LINKER:--default-script=${GENERIC_F722ZCTX_VARIANT_PATH}/ldscript.ld"
   "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
 	"LINKER:--defsym=LD_MAX_SIZE=262144"
-	"LINKER:--defsym=LD_MAX_DATA_SIZE=196608"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=262144"
   "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
   -mcpu=${GENERIC_F722ZCTX_MCU}
 )
@@ -48603,7 +49002,7 @@ target_compile_options(GENERIC_F722ZCTX_xusb_HSFS INTERFACE
 
 set(GENERIC_F722ZETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F7xx/F722Z(C-E)T_F732ZET")
 set(GENERIC_F722ZETX_MAXSIZE 524288)
-set(GENERIC_F722ZETX_MAXDATASIZE 196608)
+set(GENERIC_F722ZETX_MAXDATASIZE 262144)
 set(GENERIC_F722ZETX_MCU cortex-m7)
 set(GENERIC_F722ZETX_FPCONF "-")
 add_library(GENERIC_F722ZETX INTERFACE)
@@ -48634,7 +49033,7 @@ target_link_options(GENERIC_F722ZETX INTERFACE
   "LINKER:--default-script=${GENERIC_F722ZETX_VARIANT_PATH}/ldscript.ld"
   "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
 	"LINKER:--defsym=LD_MAX_SIZE=524288"
-	"LINKER:--defsym=LD_MAX_DATA_SIZE=196608"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=262144"
   "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
   -mcpu=${GENERIC_F722ZETX_MCU}
 )
@@ -48688,7 +49087,7 @@ target_compile_options(GENERIC_F722ZETX_xusb_HSFS INTERFACE
 
 set(GENERIC_F730R8TX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F7xx/F722R(C-E)T_F730R8T_F732RET")
 set(GENERIC_F730R8TX_MAXSIZE 65536)
-set(GENERIC_F730R8TX_MAXDATASIZE 196608)
+set(GENERIC_F730R8TX_MAXDATASIZE 262144)
 set(GENERIC_F730R8TX_MCU cortex-m7)
 set(GENERIC_F730R8TX_FPCONF "-")
 add_library(GENERIC_F730R8TX INTERFACE)
@@ -48719,7 +49118,7 @@ target_link_options(GENERIC_F730R8TX INTERFACE
   "LINKER:--default-script=${GENERIC_F730R8TX_VARIANT_PATH}/ldscript.ld"
   "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
 	"LINKER:--defsym=LD_MAX_SIZE=65536"
-	"LINKER:--defsym=LD_MAX_DATA_SIZE=196608"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=262144"
   "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
   -mcpu=${GENERIC_F730R8TX_MCU}
 )
@@ -48773,7 +49172,7 @@ target_compile_options(GENERIC_F730R8TX_xusb_HSFS INTERFACE
 
 set(GENERIC_F732RETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F7xx/F722R(C-E)T_F730R8T_F732RET")
 set(GENERIC_F732RETX_MAXSIZE 524288)
-set(GENERIC_F732RETX_MAXDATASIZE 196608)
+set(GENERIC_F732RETX_MAXDATASIZE 262144)
 set(GENERIC_F732RETX_MCU cortex-m7)
 set(GENERIC_F732RETX_FPCONF "-")
 add_library(GENERIC_F732RETX INTERFACE)
@@ -48804,7 +49203,7 @@ target_link_options(GENERIC_F732RETX INTERFACE
   "LINKER:--default-script=${GENERIC_F732RETX_VARIANT_PATH}/ldscript.ld"
   "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
 	"LINKER:--defsym=LD_MAX_SIZE=524288"
-	"LINKER:--defsym=LD_MAX_DATA_SIZE=196608"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=262144"
   "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
   -mcpu=${GENERIC_F732RETX_MCU}
 )
@@ -48858,7 +49257,7 @@ target_compile_options(GENERIC_F732RETX_xusb_HSFS INTERFACE
 
 set(GENERIC_F732ZETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F7xx/F722Z(C-E)T_F732ZET")
 set(GENERIC_F732ZETX_MAXSIZE 524288)
-set(GENERIC_F732ZETX_MAXDATASIZE 196608)
+set(GENERIC_F732ZETX_MAXDATASIZE 262144)
 set(GENERIC_F732ZETX_MCU cortex-m7)
 set(GENERIC_F732ZETX_FPCONF "-")
 add_library(GENERIC_F732ZETX INTERFACE)
@@ -48889,7 +49288,7 @@ target_link_options(GENERIC_F732ZETX INTERFACE
   "LINKER:--default-script=${GENERIC_F732ZETX_VARIANT_PATH}/ldscript.ld"
   "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
 	"LINKER:--defsym=LD_MAX_SIZE=524288"
-	"LINKER:--defsym=LD_MAX_DATA_SIZE=196608"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=262144"
   "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
   -mcpu=${GENERIC_F732ZETX_MCU}
 )
@@ -101527,7 +101926,7 @@ target_compile_options(NUCLEO_F446RE_xusb_HSFS INTERFACE
 
 set(NUCLEO_F722ZE_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F7xx/F722Z(C-E)T_F732ZET")
 set(NUCLEO_F722ZE_MAXSIZE 524288)
-set(NUCLEO_F722ZE_MAXDATASIZE 196608)
+set(NUCLEO_F722ZE_MAXDATASIZE 262144)
 set(NUCLEO_F722ZE_MCU cortex-m7)
 set(NUCLEO_F722ZE_FPCONF "-")
 add_library(NUCLEO_F722ZE INTERFACE)
@@ -101558,7 +101957,7 @@ target_link_options(NUCLEO_F722ZE INTERFACE
   "LINKER:--default-script=${NUCLEO_F722ZE_VARIANT_PATH}/ldscript.ld"
   "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
 	"LINKER:--defsym=LD_MAX_SIZE=524288"
-	"LINKER:--defsym=LD_MAX_DATA_SIZE=196608"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=262144"
   "SHELL: "
   -mcpu=${NUCLEO_F722ZE_MCU}
 )
@@ -106140,6 +106539,91 @@ target_compile_options(STEVAL_MKSBOX1V1_xusb_HSFS INTERFACE
   "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
 )
 
+# STM32C0116_DK
+# -----------------------------------------------------------------------------
+
+set(STM32C0116_DK_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P")
+set(STM32C0116_DK_MAXSIZE 32768)
+set(STM32C0116_DK_MAXDATASIZE 6144)
+set(STM32C0116_DK_MCU cortex-m0plus)
+set(STM32C0116_DK_FPCONF "-")
+add_library(STM32C0116_DK INTERFACE)
+target_compile_options(STM32C0116_DK INTERFACE
+  "SHELL:-DSTM32C011xx  -D__CORTEX_SC=0"
+  "SHELL:"
+  "SHELL:"
+  "SHELL: "
+  -mcpu=${STM32C0116_DK_MCU}
+)
+target_compile_definitions(STM32C0116_DK INTERFACE
+  "STM32C0xx"
+	"ARDUINO_STM32C0116_DK"
+	"BOARD_NAME=\"STM32C0116_DK\""
+	"BOARD_ID=STM32C0116_DK"
+	"VARIANT_H=\"variant_STM32C0116_DK.h\""
+)
+target_include_directories(STM32C0116_DK INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/
+  ${STM32C0116_DK_VARIANT_PATH}
+)
+
+target_link_options(STM32C0116_DK INTERFACE
+  "LINKER:--default-script=${STM32C0116_DK_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=32768"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=6144"
+  "SHELL: "
+  -mcpu=${STM32C0116_DK_MCU}
+)
+target_link_libraries(STM32C0116_DK INTERFACE
+  arm_cortexM0l_math
+)
+
+add_library(STM32C0116_DK_serial_disabled INTERFACE)
+target_compile_options(STM32C0116_DK_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(STM32C0116_DK_serial_generic INTERFACE)
+target_compile_options(STM32C0116_DK_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(STM32C0116_DK_serial_none INTERFACE)
+target_compile_options(STM32C0116_DK_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(STM32C0116_DK_usb_CDC INTERFACE)
+target_compile_options(STM32C0116_DK_usb_CDC INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(STM32C0116_DK_usb_CDCgen INTERFACE)
+target_compile_options(STM32C0116_DK_usb_CDCgen INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(STM32C0116_DK_usb_HID INTERFACE)
+target_compile_options(STM32C0116_DK_usb_HID INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(STM32C0116_DK_usb_none INTERFACE)
+target_compile_options(STM32C0116_DK_usb_none INTERFACE
+  "SHELL:"
+)
+add_library(STM32C0116_DK_xusb_FS INTERFACE)
+target_compile_options(STM32C0116_DK_xusb_FS INTERFACE
+  "SHELL:"
+)
+add_library(STM32C0116_DK_xusb_HS INTERFACE)
+target_compile_options(STM32C0116_DK_xusb_HS INTERFACE
+  "SHELL:-DUSE_USB_HS"
+)
+add_library(STM32C0116_DK_xusb_HSFS INTERFACE)
+target_compile_options(STM32C0116_DK_xusb_HSFS INTERFACE
+  "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
 # STM32C0316_DK
 # -----------------------------------------------------------------------------
 
diff --git a/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/CMakeLists.txt b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/CMakeLists.txt
index 2a4d55b6b1..482e0b8588 100644
--- a/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/CMakeLists.txt
+++ b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/CMakeLists.txt
@@ -22,6 +22,7 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL
   generic_clock.c
   PeripheralPins.c
   variant_generic.cpp
+  variant_STM32C0116_DK.cpp
 )
 target_link_libraries(variant_bin PUBLIC variant_usage)
 
diff --git a/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/variant_STM32C0116_DK.cpp b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/variant_STM32C0116_DK.cpp
new file mode 100644
index 0000000000..5f29256d20
--- /dev/null
+++ b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/variant_STM32C0116_DK.cpp
@@ -0,0 +1,102 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#if defined(ARDUINO_STM32C0116_DK)
+#include "pins_arduino.h"
+#include "stm32yyxx_ll_utils.h"
+
+// Digital PinName array
+const PinName digitalPin[] = {
+  PA_0,   // D0/A0
+  PA_1,   // D1/A1
+  PA_2,   // D2/A2
+  PA_3,   // D3/A3
+  PA_4,   // D4/A4
+  PA_5,   // D5/A5
+  PA_6,   // D6/A6
+  PA_7,   // D7/A7
+  PA_8,   // D8/A8
+  PA_11,  // D9/A9
+  PA_12,  // D10/A10
+  PA_13,  // D11/A11
+  PA_14,  // D12/A12
+  PB_6,   // D13
+  PB_7,   // D14
+  PC_14,  // D15
+  PC_15,  // D16
+  PF_2,   // D17
+  PA_9_R, // D18
+  PA_10_R // D19
+};
+
+// Analog (Ax) pin number array
+const uint32_t analogInputPin[] = {
+  0,  // A0,  PA0
+  1,  // A1,  PA1
+  2,  // A2,  PA2
+  3,  // A3,  PA3
+  4,  // A4,  PA4
+  5,  // A5,  PA5
+  6,  // A6,  PA6
+  7,  // A7,  PA7
+  8,  // A8,  PA8
+  9,  // A9,  PA11
+  10, // A10, PA12
+  11, // A11, PA13
+  12  // A12, PA14
+};
+
+// ----------------------------------------------------------------------------
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  * @brief  System Clock Configuration
+  * @param  None
+  * @retval None
+  */
+WEAK void SystemClock_Config(void)
+{
+  LL_FLASH_SetLatency(LL_FLASH_LATENCY_1);
+
+  /* HSI configuration and activation */
+  LL_RCC_HSI_Enable();
+  while (LL_RCC_HSI_IsReady() != 1) {
+  }
+
+  LL_RCC_HSI_SetCalibTrimming(64);
+  LL_RCC_SetHSIDiv(LL_RCC_HSI_DIV_1);
+  /* Set AHB prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  /* Sysclk activation on the HSI */
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
+  while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {
+  }
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(48000000);
+
+  /* Update the time base */
+  if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) {
+    Error_Handler();
+  }
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ARDUINO_STM32C0116_DK */
diff --git a/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/variant_STM32C0116_DK.h b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/variant_STM32C0116_DK.h
new file mode 100644
index 0000000000..fda49f2a3a
--- /dev/null
+++ b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P/variant_STM32C0116_DK.h
@@ -0,0 +1,162 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#pragma once
+
+/*----------------------------------------------------------------------------
+ *        STM32 pins number
+ *----------------------------------------------------------------------------*/
+#define PA0                     PIN_A0
+#define PA1                     PIN_A1
+#define PA2                     PIN_A2  // USART2_TX Grove connector
+#define PA3                     PIN_A3  // USART2_RX Grove connector
+#define PA4                     PIN_A4
+#define PA5                     PIN_A5
+#define PA6                     PIN_A6
+#define PA7                     PIN_A7
+#define PA8                     PIN_A8  // Joystick
+#define PA11                    PIN_A9
+#define PA12                    PIN_A10
+#define PA13                    PIN_A11 // SWDIO
+#define PA14                    PIN_A12 // SWCLK
+#define PB6                     13      // LED
+#define PB7                     14
+#define PC14                    15
+#define PC15                    16
+#define PF2                     17      // RESET or USER button
+#define PA9_R                   18      // VCP TX
+#define PA10_R                  19      // VCP RX
+
+// Alternate pins number
+#define PA0_ALT1                (PA0  | ALT1)
+#define PA1_ALT1                (PA1  | ALT1)
+#define PA2_ALT1                (PA2  | ALT1)
+#define PA3_ALT1                (PA3  | ALT1)
+#define PA4_ALT1                (PA4  | ALT1)
+#define PA4_ALT2                (PA4  | ALT2)
+#define PA5_ALT1                (PA5  | ALT1)
+#define PA6_ALT1                (PA6  | ALT1)
+#define PA7_ALT1                (PA7  | ALT1)
+#define PA7_ALT2                (PA7  | ALT2)
+#define PA7_ALT3                (PA7  | ALT3)
+#define PA8_ALT1                (PA8  | ALT1)
+#define PA8_ALT2                (PA8  | ALT2)
+#define PA8_ALT3                (PA8  | ALT3)
+#define PA8_ALT4                (PA8  | ALT4)
+#define PA8_ALT5                (PA8  | ALT5)
+#define PB6_ALT1                (PB6  | ALT1)
+#define PB6_ALT2                (PB6  | ALT2)
+#define PB6_ALT3                (PB6  | ALT3)
+#define PB6_ALT4                (PB6  | ALT4)
+#define PB6_ALT5                (PB6  | ALT5)
+#define PB7_ALT1                (PB7  | ALT1)
+#define PB7_ALT2                (PB7  | ALT2)
+#define PB7_ALT3                (PB7  | ALT3)
+#define PB7_ALT4                (PB7  | ALT4)
+#define PC14_ALT1               (PC14 | ALT1)
+
+#define NUM_DIGITAL_PINS        20
+#define NUM_REMAP_PINS          2
+#define NUM_ANALOG_INPUTS       13
+
+// On-board LED pin number
+#define LED_GREEN               PB6
+#ifndef LED_BUILTIN
+  #define LED_BUILTIN           LED_GREEN
+#endif
+
+// On-board user button
+#ifndef USER_BTN
+  #define USER_BTN              PF2
+#endif
+
+// SPI definitions
+#ifndef PIN_SPI_SS
+  #define PIN_SPI_SS            PA4
+#endif
+#ifndef PIN_SPI_SS1
+  #define PIN_SPI_SS1           PA8
+#endif
+#ifndef PIN_SPI_SS2
+  #define PIN_SPI_SS2           PA14
+#endif
+#ifndef PIN_SPI_SS3
+  #define PIN_SPI_SS3           PNUM_NOT_DEFINED
+#endif
+#ifndef PIN_SPI_MOSI
+  #define PIN_SPI_MOSI          PA7
+#endif
+#ifndef PIN_SPI_MISO
+  #define PIN_SPI_MISO          PA6
+#endif
+#ifndef PIN_SPI_SCK
+  #define PIN_SPI_SCK           PA5
+#endif
+
+// I2C definitions
+#ifndef PIN_WIRE_SDA
+  #define PIN_WIRE_SDA          PC14
+#endif
+#ifndef PIN_WIRE_SCL
+  #define PIN_WIRE_SCL          PB7
+#endif
+
+// Timer Definitions
+// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin
+#ifndef TIMER_TONE
+  #define TIMER_TONE            TIM14
+#endif
+#ifndef TIMER_SERVO
+  #define TIMER_SERVO           TIM16
+#endif
+
+// UART Definitions
+#ifndef SERIAL_UART_INSTANCE
+  #define SERIAL_UART_INSTANCE  1
+#endif
+
+// Default pin used for generic 'Serial' instance
+// Mandatory for Firmata
+#ifndef PIN_SERIAL_RX
+  #define PIN_SERIAL_RX         PA10_R
+#endif
+#ifndef PIN_SERIAL_TX
+  #define PIN_SERIAL_TX         PA9_R
+#endif
+
+/*----------------------------------------------------------------------------
+ *        Arduino objects - C++ only
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+  // These serial port names are intended to allow libraries and architecture-neutral
+  // sketches to automatically default to the correct port name for a particular type
+  // of use.  For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN,
+  // the first hardware serial port whose RX/TX pins are not dedicated to another use.
+  //
+  // SERIAL_PORT_MONITOR        Port which normally prints to the Arduino Serial Monitor
+  //
+  // SERIAL_PORT_USBVIRTUAL     Port which is USB virtual serial
+  //
+  // SERIAL_PORT_LINUXBRIDGE    Port which connects to a Linux system via Bridge library
+  //
+  // SERIAL_PORT_HARDWARE       Hardware serial port, physical RX & TX pins.
+  //
+  // SERIAL_PORT_HARDWARE_OPEN  Hardware serial ports which are open for use.  Their RX & TX
+  //                            pins are NOT connected to anything by default.
+  #ifndef SERIAL_PORT_MONITOR
+    #define SERIAL_PORT_MONITOR   Serial
+  #endif
+  #ifndef SERIAL_PORT_HARDWARE
+    #define SERIAL_PORT_HARDWARE  Serial
+  #endif
+#endif