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TNorthoverTNorthover
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ARM-NEON: make type modifiers orthogonal and allow multiple modifiers.
The modifier system used to mutate types on NEON intrinsic definitions had a separate letter for all kinds of transformations that might be needed, and we were quite quickly running out of letters to use. This patch converts to a much smaller set of orthogonal modifiers that can be applied together to achieve the desired effect. When merging with downstream it is likely to cause a conflict with any local modifications to the .td files. There is a new script in utils/convert_arm_neon.py that was used to convert all .td definitions and I would suggest running it on the last downstream version of those files before this commit rather than resolving conflicts manually.
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‎clang/include/clang/Basic/arm_fp16.td

Lines changed: 83 additions & 83 deletions
Original file line numberDiff line numberDiff line change
@@ -17,118 +17,118 @@ include "arm_neon_incl.td"
1717
let ArchGuard = "defined(__ARM_FEATURE_FP16_SCALAR_ARITHMETIC) && defined(__aarch64__)" in {
1818

1919
// Negate
20-
def VNEGSH : SInst<"vneg", "ss", "Sh">;
20+
def VNEGSH : SInst<"vneg", "11", "Sh">;
2121

2222
// Reciprocal/Sqrt
23-
def SCALAR_FRECPSH : IInst<"vrecps", "sss", "Sh">;
24-
def FSQRTSH : SInst<"vsqrt", "ss", "Sh">;
25-
def SCALAR_FRSQRTSH : IInst<"vrsqrts", "sss", "Sh">;
23+
def SCALAR_FRECPSH : IInst<"vrecps", "111", "Sh">;
24+
def FSQRTSH : SInst<"vsqrt", "11", "Sh">;
25+
def SCALAR_FRSQRTSH : IInst<"vrsqrts", "111", "Sh">;
2626

2727
// Reciprocal Estimate
28-
def SCALAR_FRECPEH : IInst<"vrecpe", "ss", "Sh">;
28+
def SCALAR_FRECPEH : IInst<"vrecpe", "11", "Sh">;
2929

3030
// Reciprocal Exponent
31-
def SCALAR_FRECPXH : IInst<"vrecpx", "ss", "Sh">;
31+
def SCALAR_FRECPXH : IInst<"vrecpx", "11", "Sh">;
3232

3333
// Reciprocal Square Root Estimate
34-
def SCALAR_FRSQRTEH : IInst<"vrsqrte", "ss", "Sh">;
34+
def SCALAR_FRSQRTEH : IInst<"vrsqrte", "11", "Sh">;
3535

3636
// Rounding
37-
def FRINTZ_S64H : SInst<"vrnd", "ss", "Sh">;
38-
def FRINTA_S64H : SInst<"vrnda", "ss", "Sh">;
39-
def FRINTI_S64H : SInst<"vrndi", "ss", "Sh">;
40-
def FRINTM_S64H : SInst<"vrndm", "ss", "Sh">;
41-
def FRINTN_S64H : SInst<"vrndn", "ss", "Sh">;
42-
def FRINTP_S64H : SInst<"vrndp", "ss", "Sh">;
43-
def FRINTX_S64H : SInst<"vrndx", "ss", "Sh">;
37+
def FRINTZ_S64H : SInst<"vrnd", "11", "Sh">;
38+
def FRINTA_S64H : SInst<"vrnda", "11", "Sh">;
39+
def FRINTI_S64H : SInst<"vrndi", "11", "Sh">;
40+
def FRINTM_S64H : SInst<"vrndm", "11", "Sh">;
41+
def FRINTN_S64H : SInst<"vrndn", "11", "Sh">;
42+
def FRINTP_S64H : SInst<"vrndp", "11", "Sh">;
43+
def FRINTX_S64H : SInst<"vrndx", "11", "Sh">;
4444

4545
// Conversion
46-
def SCALAR_SCVTFSH : SInst<"vcvth_f16", "Ys", "sUs">;
47-
def SCALAR_SCVTFSH1 : SInst<"vcvth_f16", "Ys", "iUi">;
48-
def SCALAR_SCVTFSH2 : SInst<"vcvth_f16", "Ys", "lUl">;
49-
def SCALAR_FCVTZSH : SInst<"vcvt_s16", "$s", "Sh">;
50-
def SCALAR_FCVTZSH1 : SInst<"vcvt_s32", "Is", "Sh">;
51-
def SCALAR_FCVTZSH2 : SInst<"vcvt_s64", "Ls", "Sh">;
52-
def SCALAR_FCVTZUH : SInst<"vcvt_u16", "bs", "Sh">;
53-
def SCALAR_FCVTZUH1 : SInst<"vcvt_u32", "Us", "Sh">;
54-
def SCALAR_FCVTZUH2 : SInst<"vcvt_u64", "Os", "Sh">;
55-
def SCALAR_FCVTASH : SInst<"vcvta_s16", "$s", "Sh">;
56-
def SCALAR_FCVTASH1 : SInst<"vcvta_s32", "Is", "Sh">;
57-
def SCALAR_FCVTASH2 : SInst<"vcvta_s64", "Ls", "Sh">;
58-
def SCALAR_FCVTAUH : SInst<"vcvta_u16", "bs", "Sh">;
59-
def SCALAR_FCVTAUH1 : SInst<"vcvta_u32", "Us", "Sh">;
60-
def SCALAR_FCVTAUH2 : SInst<"vcvta_u64", "Os", "Sh">;
61-
def SCALAR_FCVTMSH : SInst<"vcvtm_s16", "$s", "Sh">;
62-
def SCALAR_FCVTMSH1 : SInst<"vcvtm_s32", "Is", "Sh">;
63-
def SCALAR_FCVTMSH2 : SInst<"vcvtm_s64", "Ls", "Sh">;
64-
def SCALAR_FCVTMUH : SInst<"vcvtm_u16", "bs", "Sh">;
65-
def SCALAR_FCVTMUH1 : SInst<"vcvtm_u32", "Us", "Sh">;
66-
def SCALAR_FCVTMUH2 : SInst<"vcvtm_u64", "Os", "Sh">;
67-
def SCALAR_FCVTNSH : SInst<"vcvtn_s16", "$s", "Sh">;
68-
def SCALAR_FCVTNSH1 : SInst<"vcvtn_s32", "Is", "Sh">;
69-
def SCALAR_FCVTNSH2 : SInst<"vcvtn_s64", "Ls", "Sh">;
70-
def SCALAR_FCVTNUH : SInst<"vcvtn_u16", "bs", "Sh">;
71-
def SCALAR_FCVTNUH1 : SInst<"vcvtn_u32", "Us", "Sh">;
72-
def SCALAR_FCVTNUH2 : SInst<"vcvtn_u64", "Os", "Sh">;
73-
def SCALAR_FCVTPSH : SInst<"vcvtp_s16", "$s", "Sh">;
74-
def SCALAR_FCVTPSH1 : SInst<"vcvtp_s32", "Is", "Sh">;
75-
def SCALAR_FCVTPSH2 : SInst<"vcvtp_s64", "Ls", "Sh">;
76-
def SCALAR_FCVTPUH : SInst<"vcvtp_u16", "bs", "Sh">;
77-
def SCALAR_FCVTPUH1 : SInst<"vcvtp_u32", "Us", "Sh">;
78-
def SCALAR_FCVTPUH2 : SInst<"vcvtp_u64", "Os", "Sh">;
46+
def SCALAR_SCVTFSH : SInst<"vcvth_f16", "(1F)(1!)", "sUs">;
47+
def SCALAR_SCVTFSH1 : SInst<"vcvth_f16", "(1F<)(1!)", "iUi">;
48+
def SCALAR_SCVTFSH2 : SInst<"vcvth_f16", "(1F<<)(1!)", "lUl">;
49+
def SCALAR_FCVTZSH : SInst<"vcvt_s16", "(1S)1", "Sh">;
50+
def SCALAR_FCVTZSH1 : SInst<"vcvt_s32", "(1S>)1", "Sh">;
51+
def SCALAR_FCVTZSH2 : SInst<"vcvt_s64", "(1S>>)1", "Sh">;
52+
def SCALAR_FCVTZUH : SInst<"vcvt_u16", "(1U)1", "Sh">;
53+
def SCALAR_FCVTZUH1 : SInst<"vcvt_u32", "(1U>)1", "Sh">;
54+
def SCALAR_FCVTZUH2 : SInst<"vcvt_u64", "(1U>>)1", "Sh">;
55+
def SCALAR_FCVTASH : SInst<"vcvta_s16", "(1S)1", "Sh">;
56+
def SCALAR_FCVTASH1 : SInst<"vcvta_s32", "(1S>)1", "Sh">;
57+
def SCALAR_FCVTASH2 : SInst<"vcvta_s64", "(1S>>)1", "Sh">;
58+
def SCALAR_FCVTAUH : SInst<"vcvta_u16", "(1U)1", "Sh">;
59+
def SCALAR_FCVTAUH1 : SInst<"vcvta_u32", "(1U>)1", "Sh">;
60+
def SCALAR_FCVTAUH2 : SInst<"vcvta_u64", "(1U>>)1", "Sh">;
61+
def SCALAR_FCVTMSH : SInst<"vcvtm_s16", "(1S)1", "Sh">;
62+
def SCALAR_FCVTMSH1 : SInst<"vcvtm_s32", "(1S>)1", "Sh">;
63+
def SCALAR_FCVTMSH2 : SInst<"vcvtm_s64", "(1S>>)1", "Sh">;
64+
def SCALAR_FCVTMUH : SInst<"vcvtm_u16", "(1U)1", "Sh">;
65+
def SCALAR_FCVTMUH1 : SInst<"vcvtm_u32", "(1U>)1", "Sh">;
66+
def SCALAR_FCVTMUH2 : SInst<"vcvtm_u64", "(1U>>)1", "Sh">;
67+
def SCALAR_FCVTNSH : SInst<"vcvtn_s16", "(1S)1", "Sh">;
68+
def SCALAR_FCVTNSH1 : SInst<"vcvtn_s32", "(1S>)1", "Sh">;
69+
def SCALAR_FCVTNSH2 : SInst<"vcvtn_s64", "(1S>>)1", "Sh">;
70+
def SCALAR_FCVTNUH : SInst<"vcvtn_u16", "(1U)1", "Sh">;
71+
def SCALAR_FCVTNUH1 : SInst<"vcvtn_u32", "(1U>)1", "Sh">;
72+
def SCALAR_FCVTNUH2 : SInst<"vcvtn_u64", "(1U>>)1", "Sh">;
73+
def SCALAR_FCVTPSH : SInst<"vcvtp_s16", "(1S)1", "Sh">;
74+
def SCALAR_FCVTPSH1 : SInst<"vcvtp_s32", "(1S>)1", "Sh">;
75+
def SCALAR_FCVTPSH2 : SInst<"vcvtp_s64", "(1S>>)1", "Sh">;
76+
def SCALAR_FCVTPUH : SInst<"vcvtp_u16", "(1U)1", "Sh">;
77+
def SCALAR_FCVTPUH1 : SInst<"vcvtp_u32", "(1U>)1", "Sh">;
78+
def SCALAR_FCVTPUH2 : SInst<"vcvtp_u64", "(1U>>)1", "Sh">;
7979
let isVCVT_N = 1 in {
80-
def SCALAR_SCVTFSHO : SInst<"vcvth_n_f16", "Ysi", "sUs">;
81-
def SCALAR_SCVTFSH1O: SInst<"vcvth_n_f16", "Ysi", "iUi">;
82-
def SCALAR_SCVTFSH2O: SInst<"vcvth_n_f16", "Ysi", "lUl">;
83-
def SCALAR_FCVTZSHO : SInst<"vcvt_n_s16", "$si", "Sh">;
84-
def SCALAR_FCVTZSH1O: SInst<"vcvt_n_s32", "Isi", "Sh">;
85-
def SCALAR_FCVTZSH2O: SInst<"vcvt_n_s64", "Lsi", "Sh">;
86-
def SCALAR_FCVTZUHO : SInst<"vcvt_n_u16", "bsi", "Sh">;
87-
def SCALAR_FCVTZUH1O: SInst<"vcvt_n_u32", "Usi", "Sh">;
88-
def SCALAR_FCVTZUH2O: SInst<"vcvt_n_u64", "Osi", "Sh">;
80+
def SCALAR_SCVTFSHO : SInst<"vcvth_n_f16", "(1F)(1!)I", "sUs">;
81+
def SCALAR_SCVTFSH1O: SInst<"vcvth_n_f16", "(1F<)(1!)I", "iUi">;
82+
def SCALAR_SCVTFSH2O: SInst<"vcvth_n_f16", "(1F<<)(1!)I", "lUl">;
83+
def SCALAR_FCVTZSHO : SInst<"vcvt_n_s16", "(1S)1I", "Sh">;
84+
def SCALAR_FCVTZSH1O: SInst<"vcvt_n_s32", "(1S>)1I", "Sh">;
85+
def SCALAR_FCVTZSH2O: SInst<"vcvt_n_s64", "(1S>>)1I", "Sh">;
86+
def SCALAR_FCVTZUHO : SInst<"vcvt_n_u16", "(1U)1I", "Sh">;
87+
def SCALAR_FCVTZUH1O: SInst<"vcvt_n_u32", "(1U>)1I", "Sh">;
88+
def SCALAR_FCVTZUH2O: SInst<"vcvt_n_u64", "(1U>>)1I", "Sh">;
8989
}
9090
// Comparison
91-
def SCALAR_CMEQRH : SInst<"vceq", "bss", "Sh">;
92-
def SCALAR_CMEQZH : SInst<"vceqz", "bs", "Sh">;
93-
def SCALAR_CMGERH : SInst<"vcge", "bss", "Sh">;
94-
def SCALAR_CMGEZH : SInst<"vcgez", "bs", "Sh">;
95-
def SCALAR_CMGTRH : SInst<"vcgt", "bss", "Sh">;
96-
def SCALAR_CMGTZH : SInst<"vcgtz", "bs", "Sh">;
97-
def SCALAR_CMLERH : SInst<"vcle", "bss", "Sh">;
98-
def SCALAR_CMLEZH : SInst<"vclez", "bs", "Sh">;
99-
def SCALAR_CMLTH : SInst<"vclt", "bss", "Sh">;
100-
def SCALAR_CMLTZH : SInst<"vcltz", "bs", "Sh">;
91+
def SCALAR_CMEQRH : SInst<"vceq", "(1U)11", "Sh">;
92+
def SCALAR_CMEQZH : SInst<"vceqz", "(1U)1", "Sh">;
93+
def SCALAR_CMGERH : SInst<"vcge", "(1U)11", "Sh">;
94+
def SCALAR_CMGEZH : SInst<"vcgez", "(1U)1", "Sh">;
95+
def SCALAR_CMGTRH : SInst<"vcgt", "(1U)11", "Sh">;
96+
def SCALAR_CMGTZH : SInst<"vcgtz", "(1U)1", "Sh">;
97+
def SCALAR_CMLERH : SInst<"vcle", "(1U)11", "Sh">;
98+
def SCALAR_CMLEZH : SInst<"vclez", "(1U)1", "Sh">;
99+
def SCALAR_CMLTH : SInst<"vclt", "(1U)11", "Sh">;
100+
def SCALAR_CMLTZH : SInst<"vcltz", "(1U)1", "Sh">;
101101

102102
// Absolute Compare Mask Greater Than Or Equal
103-
def SCALAR_FACGEH : IInst<"vcage", "bss", "Sh">;
104-
def SCALAR_FACLEH : IInst<"vcale", "bss", "Sh">;
103+
def SCALAR_FACGEH : IInst<"vcage", "(1U)11", "Sh">;
104+
def SCALAR_FACLEH : IInst<"vcale", "(1U)11", "Sh">;
105105

106106
// Absolute Compare Mask Greater Than
107-
def SCALAR_FACGT : IInst<"vcagt", "bss", "Sh">;
108-
def SCALAR_FACLT : IInst<"vcalt", "bss", "Sh">;
107+
def SCALAR_FACGT : IInst<"vcagt", "(1U)11", "Sh">;
108+
def SCALAR_FACLT : IInst<"vcalt", "(1U)11", "Sh">;
109109

110110
// Scalar Absolute Value
111-
def SCALAR_ABSH : SInst<"vabs", "ss", "Sh">;
111+
def SCALAR_ABSH : SInst<"vabs", "11", "Sh">;
112112

113113
// Scalar Absolute Difference
114-
def SCALAR_ABDH: IInst<"vabd", "sss", "Sh">;
114+
def SCALAR_ABDH: IInst<"vabd", "111", "Sh">;
115115

116116
// Add/Sub
117-
def VADDSH : SInst<"vadd", "sss", "Sh">;
118-
def VSUBHS : SInst<"vsub", "sss", "Sh">;
117+
def VADDSH : SInst<"vadd", "111", "Sh">;
118+
def VSUBHS : SInst<"vsub", "111", "Sh">;
119119

120120
// Max/Min
121-
def VMAXHS : SInst<"vmax", "sss", "Sh">;
122-
def VMINHS : SInst<"vmin", "sss", "Sh">;
123-
def FMAXNMHS : SInst<"vmaxnm", "sss", "Sh">;
124-
def FMINNMHS : SInst<"vminnm", "sss", "Sh">;
121+
def VMAXHS : SInst<"vmax", "111", "Sh">;
122+
def VMINHS : SInst<"vmin", "111", "Sh">;
123+
def FMAXNMHS : SInst<"vmaxnm", "111", "Sh">;
124+
def FMINNMHS : SInst<"vminnm", "111", "Sh">;
125125

126126
// Multiplication/Division
127-
def VMULHS : SInst<"vmul", "sss", "Sh">;
128-
def MULXHS : SInst<"vmulx", "sss", "Sh">;
129-
def FDIVHS : SInst<"vdiv", "sss", "Sh">;
127+
def VMULHS : SInst<"vmul", "111", "Sh">;
128+
def MULXHS : SInst<"vmulx", "111", "Sh">;
129+
def FDIVHS : SInst<"vdiv", "111", "Sh">;
130130

131131
// Vector fused multiply-add operations
132-
def VFMAHS : SInst<"vfma", "ssss", "Sh">;
133-
def VFMSHS : SInst<"vfms", "ssss", "Sh">;
132+
def VFMAHS : SInst<"vfma", "1111", "Sh">;
133+
def VFMSHS : SInst<"vfms", "1111", "Sh">;
134134
}

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