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Improve RISC-V instruction enumeration
In preparation for future enhancements such as computed-goto, there is a need for flexible RISC-V instruction enumeration along with configurable features.
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‎src/decode.h

Lines changed: 152 additions & 150 deletions
Original file line numberDiff line numberDiff line change
@@ -8,157 +8,159 @@
88
#include <stdbool.h>
99
#include <stdint.h>
1010

11-
enum {
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/* RV32I Base Instruction Set */
13-
rv_insn_lui,
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rv_insn_auipc,
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rv_insn_jal,
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rv_insn_jalr,
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rv_insn_beq,
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rv_insn_bne,
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rv_insn_blt,
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rv_insn_bge,
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rv_insn_bltu,
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rv_insn_bgeu,
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rv_insn_lb,
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rv_insn_lh,
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rv_insn_lw,
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rv_insn_lbu,
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rv_insn_lhu,
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rv_insn_sb,
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rv_insn_sh,
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rv_insn_sw,
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rv_insn_addi,
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rv_insn_slti,
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rv_insn_sltiu,
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rv_insn_xori,
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rv_insn_ori,
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rv_insn_andi,
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rv_insn_slli,
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rv_insn_srli,
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rv_insn_srai,
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rv_insn_add,
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rv_insn_sub,
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rv_insn_sll,
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rv_insn_slt,
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rv_insn_sltu,
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rv_insn_xor,
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rv_insn_srl,
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rv_insn_sra,
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rv_insn_or,
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rv_insn_and,
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rv_insn_ecall,
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rv_insn_ebreak,
52-
53-
/* RISC-V Privileged Instruction */
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rv_insn_wfi,
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rv_insn_uret,
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rv_insn_sret,
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rv_insn_hret,
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rv_insn_mret,
59-
60-
#if RV32_HAS(Zifencei)
61-
/* RV32 Zifencei Standard Extension */
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rv_insn_fencei,
63-
#endif /* RV32_HAS(Zifencei) */
64-
65-
#if RV32_HAS(Zicsr)
66-
/* RV32 Zicsr Standard Extension */
67-
rv_insn_csrrw,
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rv_insn_csrrs,
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rv_insn_csrrc,
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rv_insn_csrrwi,
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rv_insn_csrrsi,
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rv_insn_csrrci,
73-
#endif /* RV32_HAS(Zicsr) */
74-
75-
#if RV32_HAS(EXT_M)
76-
/* RV32M Standard Extension */
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rv_insn_mul,
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rv_insn_mulh,
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rv_insn_mulhsu,
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rv_insn_mulhu,
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rv_insn_div,
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rv_insn_divu,
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rv_insn_rem,
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rv_insn_remu,
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#endif /* RV32_HAS(EXT_M) */
86-
87-
#if RV32_HAS(EXT_A)
88-
/* RV32A Standard Extension */
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rv_insn_lrw,
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rv_insn_scw,
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rv_insn_amoswapw,
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rv_insn_amoaddw,
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rv_insn_amoxorw,
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rv_insn_amoandw,
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rv_insn_amoorw,
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rv_insn_amominw,
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rv_insn_amomaxw,
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rv_insn_amominuw,
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rv_insn_amomaxuw,
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#endif
101-
102-
#if RV32_HAS(EXT_F)
103-
/* RV32F Standard Extension */
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rv_insn_flw,
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rv_insn_fsw,
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rv_insn_fmadds,
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rv_insn_fmsubs,
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rv_insn_fnmsubs,
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rv_insn_fnmadds,
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rv_insn_fadds,
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rv_insn_fsubs,
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rv_insn_fmuls,
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rv_insn_fdivs,
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rv_insn_fsqrts,
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rv_insn_fsgnjs,
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rv_insn_fsgnjns,
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rv_insn_fsgnjxs,
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rv_insn_fmins,
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rv_insn_fmaxs,
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rv_insn_fcvtws,
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rv_insn_fcvtwus,
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rv_insn_fmvxw,
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rv_insn_feqs,
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rv_insn_flts,
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rv_insn_fles,
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rv_insn_fclasss,
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rv_insn_fcvtsw,
128-
rv_insn_fcvtswu,
129-
rv_insn_fmvwx,
130-
#endif
11+
/* RISC-V instruction list */
12+
/* clang-format off */
13+
#define RISCV_INSN_LIST \
14+
/* RV32I Base Instruction Set */ \
15+
_(lui) \
16+
_(auipc) \
17+
_(jal) \
18+
_(jalr) \
19+
_(beq) \
20+
_(bne) \
21+
_(blt) \
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_(bge) \
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_(bltu) \
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_(bgeu) \
25+
_(lb) \
26+
_(lh) \
27+
_(lw) \
28+
_(lbu) \
29+
_(lhu) \
30+
_(sb) \
31+
_(sh) \
32+
_(sw) \
33+
_(addi) \
34+
_(slti) \
35+
_(sltiu) \
36+
_(xori) \
37+
_(ori) \
38+
_(andi) \
39+
_(slli) \
40+
_(srli) \
41+
_(srai) \
42+
_(add) \
43+
_(sub) \
44+
_(sll) \
45+
_(slt) \
46+
_(sltu) \
47+
_(xor) \
48+
_(srl) \
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_(sra) \
50+
_(or) \
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_(and) \
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_(ecall) \
53+
_(ebreak) \
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/* RISC-V Privileged Instruction */ \
55+
_(wfi) \
56+
_(uret) \
57+
_(sret) \
58+
_(hret) \
59+
_(mret) \
60+
/* RV32 Zifencei Standard Extension */ \
61+
IIF(RV32_HAS(Zifencei))( \
62+
_(fencei) \
63+
) \
64+
/* RV32 Zicsr Standard Extension */ \
65+
IIF(RV32_HAS(Zicsr))( \
66+
_(csrrw) \
67+
_(csrrs) \
68+
_(csrrc) \
69+
_(csrrwi) \
70+
_(csrrsi) \
71+
_(csrrci) \
72+
) \
73+
/* RV32M Standard Extension */ \
74+
IIF(RV32_HAS(EXT_M))( \
75+
_(mul) \
76+
_(mulh) \
77+
_(mulhsu) \
78+
_(mulhu) \
79+
_(div) \
80+
_(divu) \
81+
_(rem) \
82+
_(remu) \
83+
) \
84+
/* RV32A Standard Extension */ \
85+
IIF(RV32_HAS(EXT_A))( \
86+
_(lrw) \
87+
_(scw) \
88+
_(amoswapw) \
89+
_(amoaddw) \
90+
_(amoxorw) \
91+
_(amoandw) \
92+
_(amoorw) \
93+
_(amominw) \
94+
_(amomaxw) \
95+
_(amominuw) \
96+
_(amomaxuw) \
97+
) \
98+
/* RV32F Standard Extension */ \
99+
IIF(RV32_HAS(EXT_F))( \
100+
_(flw) \
101+
_(fsw) \
102+
_(fmadds) \
103+
_(fmsubs) \
104+
_(fnmsubs) \
105+
_(fnmadds) \
106+
_(fadds) \
107+
_(fsubs) \
108+
_(fmuls) \
109+
_(fdivs) \
110+
_(fsqrts) \
111+
_(fsgnjs) \
112+
_(fsgnjns) \
113+
_(fsgnjxs) \
114+
_(fmins) \
115+
_(fmaxs) \
116+
_(fcvtws) \
117+
_(fcvtwus) \
118+
_(fmvxw) \
119+
_(feqs) \
120+
_(flts) \
121+
_(fles) \
122+
_(fclasss) \
123+
_(fcvtsw) \
124+
_(fcvtswu) \
125+
_(fmvwx) \
126+
) \
127+
/* RV32C Standard Extension */ \
128+
IIF(RV32_HAS(EXT_C))( \
129+
_(caddi4spn) \
130+
_(clw) \
131+
_(csw) \
132+
_(cnop) \
133+
_(caddi) \
134+
_(cjal) \
135+
_(cli) \
136+
_(caddi16sp) \
137+
_(clui) \
138+
_(csrli) \
139+
_(csrai) \
140+
_(candi) \
141+
_(csub) \
142+
_(cxor) \
143+
_(cor) \
144+
_(cand) \
145+
_(cj) \
146+
_(cbeqz) \
147+
_(cbnez) \
148+
_(cslli) \
149+
_(clwsp) \
150+
_(cjr) \
151+
_(cmv) \
152+
_(cebreak) \
153+
_(cjalr) \
154+
_(cadd) \
155+
_(cswsp) \
156+
)
157+
/* clang-format on */
131158

132-
#if RV32_HAS(EXT_C)
133-
/* RV32C Standard Extension */
134-
rv_insn_caddi4spn,
135-
rv_insn_clw,
136-
rv_insn_csw,
137-
rv_insn_cnop,
138-
rv_insn_caddi,
139-
rv_insn_cjal,
140-
rv_insn_cli,
141-
rv_insn_caddi16sp,
142-
rv_insn_clui,
143-
rv_insn_csrli,
144-
rv_insn_csrai,
145-
rv_insn_candi,
146-
rv_insn_csub,
147-
rv_insn_cxor,
148-
rv_insn_cor,
149-
rv_insn_cand,
150-
rv_insn_cj,
151-
rv_insn_cbeqz,
152-
rv_insn_cbnez,
153-
rv_insn_cslli,
154-
rv_insn_clwsp,
155-
rv_insn_cjr,
156-
rv_insn_cmv,
157-
rv_insn_cebreak,
158-
rv_insn_cjalr,
159-
rv_insn_cadd,
160-
rv_insn_cswsp,
161-
#endif
159+
/* IR list */
160+
enum {
161+
#define _(inst) rv_insn_##inst,
162+
RISCV_INSN_LIST
163+
#undef _
162164
};
163165

164166
/* clang-format off */

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