Implement RVV integer extension instructions

Add vzext.vf{2,4,8} and vsext.vf{2,4,8} (V 1.0 section 11.3), which widen
a narrow source element into a full SEW-wide destination element.

The overlap rule here is not the one implemented by
rvv_cross_eew_overlap_illegal(): for a destination whose EEW exceeds the
source EEW, section 5.2 requires the source EMUL to be at least 1 and the
overlap to sit in the highest-numbered part of the destination group. The
check is therefore spelled out in the execution helper.

Source EMUL is compared against 1 through rvv_lmul_ratio() rather than the
register span, because rvv_eew_reg_span() clamps a fractional EMUL to a
span of one register.

Author: alanhc

src/decode.h

@@ -752,6 +752,12 @@ enum op_field {
         _(vmsif_m, 0, 4, 0, ENC(rs1, rs2, vd))            \
         _(viota_m, 0, 4, 0, ENC(rs1, rs2, vd))            \
         _(vid_v, 0, 4, 0, ENC(rs1, rs2, vd))            \
+        _(vzext_vf2, 0, 4, 0, ENC(rs1, rs2, vd))            \
+        _(vsext_vf2, 0, 4, 0, ENC(rs1, rs2, vd))            \
+        _(vzext_vf4, 0, 4, 0, ENC(rs1, rs2, vd))            \
+        _(vsext_vf4, 0, 4, 0, ENC(rs1, rs2, vd))            \
+        _(vzext_vf8, 0, 4, 0, ENC(rs1, rs2, vd))            \
+        _(vsext_vf8, 0, 4, 0, ENC(rs1, rs2, vd))            \
         /* OPF */                                         \
         _(vfadd_vv, 0, 4, 0, ENC(rs1, rs2, vd))           \
         _(vfadd_vf, 0, 4, 0, ENC(rs1, rs2, vd))           \

src/decode_v.c

@@ -983,11 +983,39 @@ static inline bool op_010010(rv_insn_t *ir, const uint32_t insn)
         /* FIXME: Implement the decoding for VFUNARY0. */
         return false;
     case 2:
-        /* OPMVV / VXUNARY0 (vzext.vf{2,4,8} and vsext.vf{2,4,8}). The
-         * RVOPs for these are not implemented yet, so refuse the encoding
-         * rather than silently misdecoding it as vsbc.vxm.
+        /* OPMVV / VXUNARY0 dispatch (V 1.0 §11.3): vs1 carries the
+         * sub-opcode selecting the extension factor and signedness.
+         * Both masked (vm=0) and unmasked (vm=1) forms are permitted.
          */
-        return false;
+        switch (decode_rs1(insn)) {
+        case 0b00010:
+            decode_vvtype(ir, insn);
+            ir->opcode = rv_insn_vzext_vf8;
+            break;
+        case 0b00011:
+            decode_vvtype(ir, insn);
+            ir->opcode = rv_insn_vsext_vf8;
+            break;
+        case 0b00100:
+            decode_vvtype(ir, insn);
+            ir->opcode = rv_insn_vzext_vf4;
+            break;
+        case 0b00101:
+            decode_vvtype(ir, insn);
+            ir->opcode = rv_insn_vsext_vf4;
+            break;
+        case 0b00110:
+            decode_vvtype(ir, insn);
+            ir->opcode = rv_insn_vzext_vf2;
+            break;
+        case 0b00111:
+            decode_vvtype(ir, insn);
+            ir->opcode = rv_insn_vsext_vf2;
+            break;
+        default:
+            return false;
+        }
+        break;
     case 3:
         /* OPIVI: vsbc has no immediate form per V 1.0 §11.4 (only vvm/vxm
          * exist). Reject explicitly instead of falling through. */

src/rv32_v_constopt.c

@@ -538,6 +538,12 @@ CONSTOPT(vmsof_m, {})
 CONSTOPT(vmsif_m, {})
 CONSTOPT(viota_m, {})
 CONSTOPT(vid_v, {})
+CONSTOPT(vzext_vf2, {})
+CONSTOPT(vsext_vf2, {})
+CONSTOPT(vzext_vf4, {})
+CONSTOPT(vsext_vf4, {})
+CONSTOPT(vzext_vf8, {})
+CONSTOPT(vsext_vf8, {})
 CONSTOPT(vfadd_vv, {})
 CONSTOPT(vfadd_vf, {})
 CONSTOPT(vfredusum_vs, {})

src/rv32_v_template.c

@@ -6499,6 +6499,93 @@ RVOP(vid_v, {
     rvv_exec_vid(rv, ir, ir->vd);
 })
 
+/* Integer extension (V 1.0 §11.3): widen each SEW/factor-wide source
+ * element into a full SEW-wide destination element, either zero- or
+ * sign-extended. The source EEW is SEW/factor with EMUL = LMUL/factor,
+ * so the source group span is derived from that narrower width while the
+ * destination keeps the SEW-based span.
+ */
+static inline bool rvv_exec_int_extend(riscv_t *rv,
+                                       const rv_insn_t *ir,
+                                       uint32_t factor,
+                                       bool is_signed)
+{
+    uint32_t sew_bits = rvv_sew_bits(rv->csr_vtype);
+    uint32_t src_bits = sew_bits / factor;
+    uint32_t vlmax = rvv_vlmax(rv->csr_vtype);
+    uint64_t fill = rvv_elem_mask64(sew_bits);
+    uint8_t vma = (rv->csr_vtype >> 7) & 0x1;
+    uint8_t vta = (rv->csr_vtype >> 6) & 0x1;
+    uint32_t src_span, dest_span = rvv_group_regs(rv->csr_vtype);
+    uint32_t lmul_num, lmul_den;
+    bool src_emul_below_one;
+
+    /* EMUL of the source is (EEW/SEW)*LMUL (V 1.0 §11.3); compare it to 1
+     * without losing the fractional case, which rvv_eew_reg_span() clamps
+     * to a span of one register.
+     */
+    rvv_lmul_ratio(rv->csr_vtype, &lmul_num, &lmul_den);
+    src_emul_below_one =
+        ((uint64_t) lmul_num * src_bits) < ((uint64_t) lmul_den * sew_bits);
+
+    /* A source narrower than 8 bits has no architectural encoding; this
+     * rejects e.g. vzext.vf8 at SEW=32 (V 1.0 §11.3).
+     */
+    if (src_bits < 8)
+        return rvv_trap_illegal_state(rv, 0);
+    if (!rvv_eew_reg_span(rv, src_bits, &src_span) ||
+        !rvv_validate_data_reg(rv->csr_vtype, ir->vd) ||
+        !rvv_validate_eew_reg(rv, src_bits, ir->vs2))
+        return rvv_trap_illegal_state(rv, 0);
+    /* Per V 1.0 §5.2, a destination whose EEW exceeds the source EEW may
+     * overlap the source only when the source EMUL is at least 1 and the
+     * overlap sits in the HIGHEST-numbered part of the destination group
+     * (at LMUL=8, `vzext.vf4 v0, v6` is legal but `v0, v0` is not). This
+     * differs from the widening-arithmetic rule in
+     * rvv_cross_eew_overlap_illegal(), which pins both groups to a shared
+     * base register, so the check is spelled out here.
+     */
+    if (rvv_reg_spans_overlap(ir->vd, dest_span, ir->vs2, src_span) &&
+        (src_emul_below_one || ((ir->vs2 + src_span) != (ir->vd + dest_span))))
+        return rvv_trap_illegal_state(rv, 0);
+
+    for (uint32_t elem = rv->csr_vstart; elem < rv->csr_vl; elem++) {
+        uint64_t value;
+        if (!rvv_mask_enabled_for_elem(rv, ir, elem)) {
+            if (vma)
+                rvv_set_elem_ext(rv, ir->vd, elem, sew_bits, fill);
+            continue;
+        }
+        value = rvv_get_elem_ext(rv, ir->vs2, elem, src_bits);
+        if (is_signed)
+            value = (uint64_t) rvv_sign_extend64(value, src_bits);
+        rvv_set_elem_ext(rv, ir->vd, elem, sew_bits,
+                         value & rvv_elem_mask64(sew_bits));
+    }
+    if (vta) {
+        for (uint32_t elem = rv->csr_vl; elem < vlmax; elem++)
+            rvv_set_elem_ext(rv, ir->vd, elem, sew_bits, fill);
+    }
+
+    rv->csr_vstart = 0;
+    return true;
+}
+
+#define RVV_INT_EXTEND_OP(name, factor, is_signed)           \
+    RVOP(name, {                                             \
+        if (rvv_require_operable(rv))                        \
+            return false;                                    \
+        if (!rvv_exec_int_extend(rv, ir, factor, is_signed)) \
+            return false;                                    \
+    })
+
+RVV_INT_EXTEND_OP(vzext_vf2, 2, false)
+RVV_INT_EXTEND_OP(vsext_vf2, 2, true)
+RVV_INT_EXTEND_OP(vzext_vf4, 4, false)
+RVV_INT_EXTEND_OP(vsext_vf4, 4, true)
+RVV_INT_EXTEND_OP(vzext_vf8, 8, false)
+RVV_INT_EXTEND_OP(vsext_vf8, 8, true)
+
 #if RV32_HAS(EXT_F)
 typedef uint32_t (*rvv_fp32_binop_fn)(uint32_t lhs, uint32_t rhs);
 typedef uint32_t (*rvv_fp32_triop_fn)(uint32_t dest,

tests/rvv-smoke.S

@@ -98,6 +98,10 @@ mulfix_lhs:
 mulfix_rhs:
     .byte 0x40, 0x80, 0x40, 0x20
 
+ext_src:
+    .byte 0x7f, 0x80, 0x01, 0xff
+    .balign 2
+
 narrow16_a:
     .short 0x8000, 0x0002
 
@@ -296,6 +300,8 @@ fixed_out:
     .space 16
 wide_out:
     .space 32
+ext_out:
+    .space 32
 red_out:
     .space 16
 wide_red_out:
@@ -1813,6 +1819,82 @@ _start:
     csrr t1, vl
     assert_reg_imm t1, 4, fail_fractional
 
+    # Integer extension (V 1.0 11.3): vzext/vsext widen a narrow source
+    # element into a full SEW-wide destination.
+    li a0, 4
+    vsetvli t0, a0, e16, m1, tu, mu
+    la a1, ext_src
+    vle8.v v20, (a1)
+
+    # vzext.vf2: 0x7f,0x80,0x01,0xff -> zero-extended to 16-bit
+    vzext.vf2 v22, v20
+    la a1, ext_out
+    vse16.v v22, (a1)
+    lhu t1, 0(a1)
+    assert_reg_imm t1, 0x007f, fail_vzext_vf2
+    lhu t1, 2(a1)
+    assert_reg_imm t1, 0x0080, fail_vzext_vf2
+    lhu t1, 6(a1)
+    assert_reg_imm t1, 0x00ff, fail_vzext_vf2
+
+    # vsext.vf2: 0x80 and 0xff are negative when sign-extended
+    vsext.vf2 v22, v20
+    la a1, ext_out
+    vse16.v v22, (a1)
+    lhu t1, 0(a1)
+    assert_reg_imm t1, 0x007f, fail_vsext_vf2
+    lhu t1, 2(a1)
+    assert_reg_imm t1, 0xff80, fail_vsext_vf2
+    lhu t1, 6(a1)
+    assert_reg_imm t1, 0xffff, fail_vsext_vf2
+
+    # vf4: 8-bit source widened to 32-bit destination
+    li a0, 4
+    vsetvli t0, a0, e32, m1, tu, mu
+    la a1, ext_src
+    vle8.v v20, (a1)
+
+    vzext.vf4 v22, v20
+    la a1, ext_out
+    vse32.v v22, (a1)
+    lw t1, 0(a1)
+    assert_reg_imm t1, 0x0000007f, fail_vzext_vf4
+    lw t1, 4(a1)
+    assert_reg_imm t1, 0x00000080, fail_vzext_vf4
+
+    vsext.vf4 v22, v20
+    la a1, ext_out
+    vse32.v v22, (a1)
+    lw t1, 4(a1)
+    assert_reg_imm t1, -128, fail_vsext_vf4
+    lw t1, 12(a1)
+    assert_reg_imm t1, -1, fail_vsext_vf4
+
+    # Masked form leaves inactive elements undisturbed (vma=0). v0 bit
+    # pattern 0x5 activates elements 0 and 2 only.
+    li a0, 4
+    vsetvli t0, a0, e32, m1, tu, mu
+    la a1, ext_out
+    li t2, 0
+    sw t2, 0(a1)
+    sw t2, 4(a1)
+    sw t2, 8(a1)
+    sw t2, 12(a1)
+    vle32.v v22, (a1)
+    la a1, mask_bits
+    vle8.v v0, (a1)
+    la a1, ext_src
+    vle8.v v20, (a1)
+    vzext.vf4 v22, v20, v0.t
+    la a1, ext_out
+    vse32.v v22, (a1)
+    lw t1, 0(a1)
+    assert_reg_imm t1, 0x0000007f, fail_vzext_mask
+    lw t1, 4(a1)
+    assert_reg_imm t1, 0, fail_vzext_mask
+    lw t1, 8(a1)
+    assert_reg_imm t1, 0x00000001, fail_vzext_mask
+
     la a1, ok_msg
     li a2, ok_msg_len
     j write_and_exit_ok
@@ -1911,6 +1993,21 @@ fail_vsmul4:
 fail_vwadd:
     li a3, 0xd5
     j write_and_exit_fail
+fail_vzext_vf2:
+    li a3, 0xf1
+    j write_and_exit_fail
+fail_vsext_vf2:
+    li a3, 0xf2
+    j write_and_exit_fail
+fail_vzext_vf4:
+    li a3, 0xf3
+    j write_and_exit_fail
+fail_vsext_vf4:
+    li a3, 0xf4
+    j write_and_exit_fail
+fail_vzext_mask:
+    li a3, 0xf5
+    j write_and_exit_fail
 fail_vwmulu:
     li a3, 0xd6
     j write_and_exit_fail