Improve compliance for privileged instructions

Pass serveral privilege instruction and exceptions tests like ebreak,
misaligned load word and misaligned store word.

Moreover, the privilege instruction ecall doesn't pass the test
because it only dispatches the syscall number to corresponding handler.

Therefore, it needs to implement the exception handler with control
and status registers (CSRs).

Author: Risheng1128

README.md

@@ -86,19 +86,8 @@ Current progress of this emulator in riscv-arch-test(RV32):
     - `Zifencei`: Instruction-Fetch Fence
 * Failed Tests
     - `privilege`: RISCV Privileged Specification
-        + 2 system calls
-            * `ebreak`
+        + 1 system calls
             * `ecall`
-        + 5 misaligned CB-type instructions
-            * `misalign-beq`
-            * `misalign-bge`
-            * `misalign-bgeu`
-            * `misalign-blt`
-            * `misalign-bltu`
-        + 1 misaligned CL-type instructions
-            * `misalign-lw`
-        + 1 misaligned CS-type instructions
-            * `misalign-sw`
 * Unsupported tests (runnable but incomplete)
     - `F` Standard Extension for Single-Precision Floating-Point
 

src/emulate.c

@@ -761,7 +761,7 @@ static inline bool op_system(struct riscv_t *rv, uint32_t insn)
      *  31     20 19   15 14    12 11   7 6      0
      * |   csr   |  rs1  | funct3 |  rd  | opcode |
      */
-    const int32_t imm = dec_itype_imm(insn);
+    const int32_t funct12 = dec_funct12(insn);
     const int32_t csr = dec_csr(insn);
     const uint32_t funct3 = dec_funct3(insn);
     const uint32_t rs1 = dec_rs1(insn);
@@ -770,13 +770,13 @@ static inline bool op_system(struct riscv_t *rv, uint32_t insn)
     /* dispatch by func3 field */
     switch (funct3) {
     case 0:
-        switch (imm) { /* dispatch from imm field */
-        case 0:        /* ECALL: Environment Call */
+        switch (funct12) { /* dispatch from imm field */
+        case 0:            /* ECALL: Environment Call */
             rv->io.on_ecall(rv);
             break;
         case 1: /* EBREAK: Environment Break */
             rv->io.on_ebreak(rv);
-            break;
+            return true;
         case 0x002: /* URET: Return from handling an interrupt or exception */
         case 0x102: /* SRET */
         case 0x202: /* HRET */

src/riscv_private.h

@@ -261,6 +261,12 @@ static inline uint32_t dec_r4type_rs3(const uint32_t insn)
     return (insn & FR4_RS3) >> 27;
 }
 
+/* decode system instruction immediate (same as itype) */
+static inline uint32_t dec_funct12(const uint32_t insn)
+{
+    return ((uint32_t)(insn & FI_IMM_11_0)) >> 20;
+}
+
 /* decode csr instruction immediate (same as itype, zero extend) */
 static inline uint32_t dec_csr(const uint32_t insn)
 {

tests/arch-test-target/device/rv32i_m/privilege/Makefile.include

@@ -5,7 +5,7 @@ RUN_TARGET= $(TARGETDIR)/build/rv32emu $(<) \
 
 RISCV_GCC      ?= $(RISCV_PREFIX)gcc
 RISCV_GCC_OPTS ?= \
-    -march=rv32gc \
+    -march=rv32g \
     -mabi=ilp32 \
     -static \
     -mcmodel=medany \