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jservjserv
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Merge pull request #123 from qwe661234/wip/imporve_memory_io
Improve memory read/write
2 parents 66300d0 + 0771e4e commit 797a961

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+307
-145
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11 files changed

+307
-145
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‎.github/workflows/main.yml

+1
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@ jobs:
1717
run: |
1818
make check
1919
make tests
20+
make misalign
2021
- name: diverse configurations
2122
run: |
2223
make distclean ENABLE_EXT_C=0 check

‎Makefile

+10
Original file line numberDiff line numberDiff line change
@@ -94,6 +94,7 @@ OBJS := \
9494
riscv.o \
9595
elf.o \
9696
cache.o \
97+
mpool.o \
9798
$(OBJS_EXT) \
9899
main.o
99100

@@ -132,6 +133,15 @@ check: $(BIN)
132133
fi; \
133134
)
134135

136+
EXPECTED_aes = Dec 15 2022 16:35:12 Test results AES-128 ECB encryption: PASSED! AES-128 ECB decryption: PASSED! AES-128 CBC encryption: PASSED! AES-128 CBC decryption: PASSED! AES-128 CFB encryption: PASSED! AES-128 CFB decryption: PASSED! AES-128 OFB encryption: PASSED! AES-128 OFB decryption: PASSED! AES-128 CTR encryption: PASSED! AES-128 CTR decryption: PASSED! AES-128 XTS encryption: PASSED! AES-128 XTS decryption: PASSED! AES-128 validate CMAC : PASSED! AES-128 Poly-1305 mac : PASSED! AES-128 GCM encryption: PASSED! AES-128 GCM decryption: PASSED! AES-128 CCM encryption: PASSED! AES-128 CCM decryption: PASSED! AES-128 OCB encryption: PASSED! AES-128 OCB decryption: PASSED! AES-128 SIV encryption: PASSED! AES-128 SIV decryption: PASSED! AES-128 GCMSIV encrypt: PASSED! AES-128 GCMSIV decrypt: PASSED! AES-128 EAX encryption: PASSED! AES-128 EAX decryption: PASSED! AES-128 key wrapping : PASSED! AES-128 key unwrapping: PASSED! AES-128 FF1 encryption: PASSED! AES-128 FPE decryption: PASSED! +-> Let's do some extra tests AES-128 OCB encryption: PASSED! AES-128 OCB decryption: PASSED! AES-128 GCMSIV encrypt: PASSED! AES-128 GCMSIV decrypt: PASSED! AES-128 GCMSIV encrypt: PASSED! AES-128 GCMSIV decrypt: PASSED! AES-128 SIV encryption: PASSED! AES-128 SIV decryption: PASSED! AES-128 SIV encryption: PASSED! AES-128 SIV decryption: PASSED! AES-128 EAX encryption: PASSED! AES-128 EAX decryption: PASSED! AES-128 EAX encryption: PASSED! AES-128 EAX decryption: PASSED! AES-128 Poly-1305 mac : PASSED! inferior exit code 0
137+
misalign: $(BIN)
138+
$(Q)$(PRINTF) "Running aes.elf ... ";
139+
ifeq ($(shell $(BIN) --misalign $(OUT)/aes.elf | uniq), $(EXPECTED_aes))
140+
$(Q)$(call notice, [OK]);
141+
else
142+
$(Q)$(PRINTF) "Failed.\n";
143+
endif
144+
135145
include mk/external.mk
136146

137147
# Non-trivial demonstration programs

‎src/emulate.c

+36-100
Original file line numberDiff line numberDiff line change
@@ -90,6 +90,22 @@ static void rv_exception_default_handler(riscv_t *rv)
9090
RV_EXCEPTION_LIST
9191
#undef _
9292

93+
/* wrap load/store and insn misaligned handler
94+
* @mask_or_pc: mask for load/store and pc for insn misaligned handler.
95+
* @type: type of misaligned handler
96+
* @compress: compressed instruction or not
97+
* @IO: whether the misaligned handler is for load/store or insn.
98+
*/
99+
#define RV_EXC_MISALIGN_HANDLER(mask_or_pc, type, compress, IO) \
100+
IIF(IO) \
101+
(if (!rv->io.allow_misalign && unlikely(addr & (mask_or_pc))), \
102+
if (unlikely(insn_is_misaligned(rv->PC)))) \
103+
{ \
104+
rv->compressed = compress; \
105+
rv_except_##type##_misaligned(rv, IIF(IO)(addr, mask_or_pc)); \
106+
return false; \
107+
}
108+
93109
/* Get current time in microsecnds and update csr_time register */
94110
static inline void update_time(riscv_t *rv)
95111
{
@@ -310,11 +326,7 @@ RVOP(jal, {
310326
if (ir->rd)
311327
rv->X[ir->rd] = pc + ir->insn_len;
312328
/* check instruction misaligned */
313-
if (unlikely(insn_is_misaligned(rv->PC))) {
314-
rv->compressed = false;
315-
rv_except_insn_misaligned(rv, pc);
316-
return false;
317-
}
329+
RV_EXC_MISALIGN_HANDLER(pc, insn, false, 0);
318330
return true;
319331
})
320332

@@ -333,11 +345,7 @@ RVOP(jalr, {
333345
if (ir->rd)
334346
rv->X[ir->rd] = pc + ir->insn_len;
335347
/* check instruction misaligned */
336-
if (unlikely(insn_is_misaligned(rv->PC))) {
337-
rv->compressed = false;
338-
rv_except_insn_misaligned(rv, pc);
339-
return false;
340-
}
348+
RV_EXC_MISALIGN_HANDLER(pc, insn, false, 0);
341349
return true;
342350
})
343351

@@ -352,11 +360,7 @@ RVOP(beq, {
352360
}
353361
rv->PC += ir->imm;
354362
/* check instruction misaligned */
355-
if (unlikely(insn_is_misaligned(rv->PC))) {
356-
rv->compressed = false;
357-
rv_except_insn_misaligned(rv, pc);
358-
return false;
359-
}
363+
RV_EXC_MISALIGN_HANDLER(pc, insn, false, 0);
360364
if (ir->branch_taken)
361365
return ir->branch_taken->impl(rv, ir->branch_taken);
362366
return true;
@@ -373,11 +377,7 @@ RVOP(bne, {
373377
}
374378
rv->PC += ir->imm;
375379
/* check instruction misaligned */
376-
if (unlikely(insn_is_misaligned(rv->PC))) {
377-
rv->compressed = false;
378-
rv_except_insn_misaligned(rv, pc);
379-
return false;
380-
}
380+
RV_EXC_MISALIGN_HANDLER(pc, insn, false, 0);
381381
if (ir->branch_taken)
382382
return ir->branch_taken->impl(rv, ir->branch_taken);
383383
return true;
@@ -394,11 +394,7 @@ RVOP(blt, {
394394
}
395395
rv->PC += ir->imm;
396396
/* check instruction misaligned */
397-
if (unlikely(insn_is_misaligned(rv->PC))) {
398-
rv->compressed = false;
399-
rv_except_insn_misaligned(rv, pc);
400-
return false;
401-
}
397+
RV_EXC_MISALIGN_HANDLER(pc, insn, false, 0);
402398
if (ir->branch_taken)
403399
return ir->branch_taken->impl(rv, ir->branch_taken);
404400
return true;
@@ -415,11 +411,7 @@ RVOP(bge, {
415411
}
416412
rv->PC += ir->imm;
417413
/* check instruction misaligned */
418-
if (unlikely(insn_is_misaligned(rv->PC))) {
419-
rv->compressed = false;
420-
rv_except_insn_misaligned(rv, pc);
421-
return false;
422-
}
414+
RV_EXC_MISALIGN_HANDLER(pc, insn, false, 0);
423415
if (ir->branch_taken)
424416
return ir->branch_taken->impl(rv, ir->branch_taken);
425417
return true;
@@ -436,11 +428,7 @@ RVOP(bltu, {
436428
}
437429
rv->PC += ir->imm;
438430
/* check instruction misaligned */
439-
if (unlikely(insn_is_misaligned(rv->PC))) {
440-
rv->compressed = false;
441-
rv_except_insn_misaligned(rv, pc);
442-
return false;
443-
}
431+
RV_EXC_MISALIGN_HANDLER(pc, insn, false, 0);
444432
if (ir->branch_taken)
445433
return ir->branch_taken->impl(rv, ir->branch_taken);
446434
return true;
@@ -457,11 +445,7 @@ RVOP(bgeu, {
457445
}
458446
rv->PC += ir->imm;
459447
/* check instruction misaligned */
460-
if (unlikely(insn_is_misaligned(rv->PC))) {
461-
rv->compressed = false;
462-
rv_except_insn_misaligned(rv, pc);
463-
return false;
464-
}
448+
RV_EXC_MISALIGN_HANDLER(pc, insn, false, 0);
465449
if (ir->branch_taken)
466450
return ir->branch_taken->impl(rv, ir->branch_taken);
467451
return true;
@@ -476,22 +460,14 @@ RVOP(lb, {
476460
/* LH: Load Halfword */
477461
RVOP(lh, {
478462
const uint32_t addr = rv->X[ir->rs1] + ir->imm;
479-
if (unlikely(addr & 1)) {
480-
rv->compressed = false;
481-
rv_except_load_misaligned(rv, addr);
482-
return false;
483-
}
463+
RV_EXC_MISALIGN_HANDLER(1, load, false, 1);
484464
rv->X[ir->rd] = sign_extend_h(rv->io.mem_read_s(rv, addr));
485465
})
486466

487467
/* LW: Load Word */
488468
RVOP(lw, {
489469
const uint32_t addr = rv->X[ir->rs1] + ir->imm;
490-
if (unlikely(addr & 3)) {
491-
rv->compressed = false;
492-
rv_except_load_misaligned(rv, addr);
493-
return false;
494-
}
470+
RV_EXC_MISALIGN_HANDLER(3, load, false, 1);
495471
rv->X[ir->rd] = rv->io.mem_read_w(rv, addr);
496472
})
497473

@@ -501,11 +477,7 @@ RVOP(lbu, { rv->X[ir->rd] = rv->io.mem_read_b(rv, rv->X[ir->rs1] + ir->imm); })
501477
/* LHU: Load Halfword Unsigned */
502478
RVOP(lhu, {
503479
const uint32_t addr = rv->X[ir->rs1] + ir->imm;
504-
if (unlikely(addr & 1)) {
505-
rv->compressed = false;
506-
rv_except_load_misaligned(rv, addr);
507-
return false;
508-
}
480+
RV_EXC_MISALIGN_HANDLER(1, load, false, 1);
509481
rv->X[ir->rd] = rv->io.mem_read_s(rv, addr);
510482
})
511483

@@ -515,22 +487,14 @@ RVOP(sb, { rv->io.mem_write_b(rv, rv->X[ir->rs1] + ir->imm, rv->X[ir->rs2]); })
515487
/* SH: Store Halfword */
516488
RVOP(sh, {
517489
const uint32_t addr = rv->X[ir->rs1] + ir->imm;
518-
if (unlikely(addr & 1)) {
519-
rv->compressed = false;
520-
rv_except_store_misaligned(rv, addr);
521-
return false;
522-
}
490+
RV_EXC_MISALIGN_HANDLER(1, store, false, 1);
523491
rv->io.mem_write_s(rv, addr, rv->X[ir->rs2]);
524492
})
525493

526494
/* SW: Store Word */
527495
RVOP(sw, {
528496
const uint32_t addr = rv->X[ir->rs1] + ir->imm;
529-
if (unlikely(addr & 3)) {
530-
rv->compressed = false;
531-
rv_except_store_misaligned(rv, addr);
532-
return false;
533-
}
497+
RV_EXC_MISALIGN_HANDLER(3, store, false, 1);
534498
rv->io.mem_write_w(rv, addr, rv->X[ir->rs2]);
535499
})
536500

@@ -1088,11 +1052,7 @@ RVOP(caddi4spn, { rv->X[ir->rd] = rv->X[2] + (uint16_t) ir->imm; })
10881052
*/
10891053
RVOP(clw, {
10901054
const uint32_t addr = rv->X[ir->rs1] + (uint32_t) ir->imm;
1091-
if (unlikely(addr & 3)) {
1092-
rv->compressed = true;
1093-
rv_except_load_misaligned(rv, addr);
1094-
return false;
1095-
}
1055+
RV_EXC_MISALIGN_HANDLER(3, load, true, 1);
10961056
rv->X[ir->rd] = rv->io.mem_read_w(rv, addr);
10971057
})
10981058

@@ -1103,11 +1063,7 @@ RVOP(clw, {
11031063
*/
11041064
RVOP(csw, {
11051065
const uint32_t addr = rv->X[ir->rs1] + (uint32_t) ir->imm;
1106-
if (unlikely(addr & 3)) {
1107-
rv->compressed = true;
1108-
rv_except_store_misaligned(rv, addr);
1109-
return false;
1110-
}
1066+
RV_EXC_MISALIGN_HANDLER(3, store, true, 1);
11111067
rv->io.mem_write_w(rv, addr, rv->X[ir->rs2]);
11121068
})
11131069

@@ -1126,11 +1082,7 @@ RVOP(caddi, { rv->X[ir->rd] += (int16_t) ir->imm; })
11261082
RVOP(cjal, {
11271083
rv->X[1] = rv->PC + ir->insn_len;
11281084
rv->PC += ir->imm;
1129-
if (unlikely(rv->PC & 0x1)) {
1130-
rv->compressed = true;
1131-
rv_except_insn_misaligned(rv, rv->PC);
1132-
return false;
1133-
}
1085+
RV_EXC_MISALIGN_HANDLER(rv->PC, insn, true, 0);
11341086
return true;
11351087
})
11361088

@@ -1198,11 +1150,7 @@ RVOP(cand, { rv->X[ir->rd] = rv->X[ir->rs1] & rv->X[ir->rs2]; })
11981150
*/
11991151
RVOP(cj, {
12001152
rv->PC += ir->imm;
1201-
if (unlikely(rv->PC & 0x1)) {
1202-
rv->compressed = true;
1203-
rv_except_insn_misaligned(rv, rv->PC);
1204-
return false;
1205-
}
1153+
RV_EXC_MISALIGN_HANDLER(rv->PC, insn, true, 0);
12061154
return true;
12071155
})
12081156

@@ -1249,11 +1197,7 @@ RVOP(cslli, { rv->X[ir->rd] <<= (uint8_t) ir->imm; })
12491197
/* C.LWSP */
12501198
RVOP(clwsp, {
12511199
const uint32_t addr = rv->X[rv_reg_sp] + ir->imm;
1252-
if (unlikely(addr & 3)) {
1253-
rv->compressed = true;
1254-
rv_except_load_misaligned(rv, addr);
1255-
return false;
1256-
}
1200+
RV_EXC_MISALIGN_HANDLER(3, load, true, 1);
12571201
rv->X[ir->rd] = rv->io.mem_read_w(rv, addr);
12581202
})
12591203

@@ -1279,11 +1223,7 @@ RVOP(cjalr, {
12791223
const int32_t jump_to = rv->X[ir->rs1];
12801224
rv->X[rv_reg_ra] = rv->PC + ir->insn_len;
12811225
rv->PC = jump_to;
1282-
if (unlikely(rv->PC & 0x1)) {
1283-
rv->compressed = true;
1284-
rv_except_insn_misaligned(rv, rv->PC);
1285-
return false;
1286-
}
1226+
RV_EXC_MISALIGN_HANDLER(rv->PC, insn, true, 0);
12871227
return true;
12881228
})
12891229

@@ -1299,11 +1239,7 @@ RVOP(cadd, { rv->X[ir->rd] = rv->X[ir->rs1] + rv->X[ir->rs2]; })
12991239
/* C.SWSP */
13001240
RVOP(cswsp, {
13011241
const uint32_t addr = rv->X[2] + ir->imm;
1302-
if (unlikely(addr & 3)) {
1303-
rv->compressed = true;
1304-
rv_except_store_misaligned(rv, addr);
1305-
return false;
1306-
}
1242+
RV_EXC_MISALIGN_HANDLER(3, store, true, 1);
13071243
rv->io.mem_write_w(rv, addr, rv->X[ir->rs2]);
13081244
})
13091245
#endif

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