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Merge pull request #644 from sysprog21/fix-arm-jit
Fix JIT non-deterministic execution on Arm64
2 parents 81f4206 + c33b212 commit 7bcca9c

9 files changed

Lines changed: 315 additions & 74 deletions

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src/emulate.c

Lines changed: 16 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1212,7 +1212,14 @@ void rv_step(void *arg)
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#if RV32_HAS(JIT)
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#if RV32_HAS(T2C)
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/* executed through the tier-2 JIT compiler */
1215-
if (block->hot2) {
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if (__atomic_load_n(&block->hot2, __ATOMIC_ACQUIRE)) {
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/* Atomic load-acquire pairs with store-release in t2c_compile().
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* Ensures we see the updated block->func after observing hot2=true.
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*/
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#if defined(__aarch64__)
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/* Ensure instruction cache coherency before executing T2C code */
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__asm__ volatile("isb" ::: "memory");
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#endif
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((exec_t2c_func_t) block->func)(rv);
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prev = NULL;
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continue;
@@ -1240,6 +1247,10 @@ void rv_step(void *arg)
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*/
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if (block->hot) {
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block->n_invoke++;
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#if defined(__aarch64__)
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/* Ensure instruction cache coherency before executing JIT code */
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__asm__ volatile("isb" ::: "memory");
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#endif
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((exec_block_func_t) state->buf)(
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rv, (uintptr_t) (state->buf + block->offset));
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prev = NULL;
@@ -1251,6 +1262,10 @@ void rv_step(void *arg)
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#endif
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) {
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jit_translate(rv, block);
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#if defined(__aarch64__)
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/* Ensure instruction cache coherency before executing JIT code */
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__asm__ volatile("isb" ::: "memory");
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#endif
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((exec_block_func_t) state->buf)(
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rv, (uintptr_t) (state->buf + block->offset));
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prev = NULL;

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