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Reduce Instruction length checking
1 parent c39da6f commit 7f43836

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1 file changed

+24
-3
lines changed

1 file changed

+24
-3
lines changed

‎src/emulate.c

+24-3
Original file line numberDiff line numberDiff line change
@@ -256,9 +256,6 @@ static bool insn_is_misaligned(uint32_t pc)
256256

257257
static bool emulate(riscv_t *rv, rv_insn_t *ir)
258258
{
259-
/* check instruction is compressed or not */
260-
rv->compressed = (ir->insn_len == INSN_16);
261-
262259
switch (ir->opcode) {
263260
/* RV32I Base Instruction Set */
264261
case rv_insn_lui: /* LUI: Load Upper Immediate */
@@ -290,6 +287,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
290287
rv->X[ir->rd] = pc + ir->insn_len;
291288
/* check instruction misaligned */
292289
if (insn_is_misaligned(rv->PC)) {
290+
rv->compressed = false;
293291
rv_except_insn_misaligned(rv, pc);
294292
return false;
295293
}
@@ -312,6 +310,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
312310
rv->X[ir->rd] = pc + ir->insn_len;
313311
/* check instruction misaligned */
314312
if (insn_is_misaligned(rv->PC)) {
313+
rv->compressed = false;
315314
rv_except_insn_misaligned(rv, pc);
316315
return false;
317316
}
@@ -324,6 +323,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
324323
rv->PC += ir->imm;
325324
/* check instruction misaligned */
326325
if (insn_is_misaligned(rv->PC)) {
326+
rv->compressed = false;
327327
rv_except_insn_misaligned(rv, pc);
328328
return false;
329329
}
@@ -338,6 +338,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
338338
rv->PC += ir->imm;
339339
/* check instruction misaligned */
340340
if (insn_is_misaligned(rv->PC)) {
341+
rv->compressed = false;
341342
rv_except_insn_misaligned(rv, pc);
342343
return false;
343344
}
@@ -352,6 +353,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
352353
rv->PC += ir->imm;
353354
/* check instruction misaligned */
354355
if (insn_is_misaligned(rv->PC)) {
356+
rv->compressed = false;
355357
rv_except_insn_misaligned(rv, pc);
356358
return false;
357359
}
@@ -366,6 +368,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
366368
rv->PC += ir->imm;
367369
/* check instruction misaligned */
368370
if (insn_is_misaligned(rv->PC)) {
371+
rv->compressed = false;
369372
rv_except_insn_misaligned(rv, pc);
370373
return false;
371374
}
@@ -380,6 +383,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
380383
rv->PC += ir->imm;
381384
/* check instruction misaligned */
382385
if (insn_is_misaligned(rv->PC)) {
386+
rv->compressed = false;
383387
rv_except_insn_misaligned(rv, pc);
384388
return false;
385389
}
@@ -394,6 +398,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
394398
rv->PC += ir->imm;
395399
/* check instruction misaligned */
396400
if (insn_is_misaligned(rv->PC)) {
401+
rv->compressed = false;
397402
rv_except_insn_misaligned(rv, pc);
398403
return false;
399404
}
@@ -409,6 +414,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
409414
case rv_insn_lh: { /* LH: Load Halfword */
410415
const uint32_t addr = rv->X[ir->rs1] + ir->imm;
411416
if (addr & 1) {
417+
rv->compressed = false;
412418
rv_except_load_misaligned(rv, addr);
413419
return false;
414420
}
@@ -418,6 +424,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
418424
case rv_insn_lw: { /* LW: Load Word */
419425
const uint32_t addr = rv->X[ir->rs1] + ir->imm;
420426
if (addr & 3) {
427+
rv->compressed = false;
421428
rv_except_load_misaligned(rv, addr);
422429
return false;
423430
}
@@ -430,6 +437,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
430437
case rv_insn_lhu: { /* LHU: Load Halfword Unsigned */
431438
const uint32_t addr = rv->X[ir->rs1] + ir->imm;
432439
if (addr & 1) {
440+
rv->compressed = false;
433441
rv_except_load_misaligned(rv, addr);
434442
return false;
435443
}
@@ -442,6 +450,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
442450
case rv_insn_sh: { /* SH: Store Halfword */
443451
const uint32_t addr = rv->X[ir->rs1] + ir->imm;
444452
if (addr & 1) {
453+
rv->compressed = false;
445454
rv_except_store_misaligned(rv, addr);
446455
return false;
447456
}
@@ -451,6 +460,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
451460
case rv_insn_sw: { /* SW: Store Word */
452461
const uint32_t addr = rv->X[ir->rs1] + ir->imm;
453462
if (addr & 3) {
463+
rv->compressed = false;
454464
rv_except_store_misaligned(rv, addr);
455465
return false;
456466
}
@@ -541,9 +551,11 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
541551
rv->X[ir->rd] = rv->X[ir->rs1] & rv->X[ir->rs2];
542552
break;
543553
case rv_insn_ecall: /* ECALL: Environment Call */
554+
rv->compressed = false;
544555
rv->io.on_ecall(rv);
545556
return true;
546557
case rv_insn_ebreak: /* EBREAK: Environment Break */
558+
rv->compressed = false;
547559
rv->io.on_ebreak(rv);
548560
return true;
549561
case rv_insn_wfi: /* WFI: Wait for Interrupt */
@@ -931,6 +943,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
931943
*/
932944
const uint32_t addr = rv->X[ir->rs1] + (uint32_t) ir->imm;
933945
if (addr & 3) {
946+
rv->compressed = true;
934947
rv_except_load_misaligned(rv, addr);
935948
return false;
936949
}
@@ -945,6 +958,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
945958
*/
946959
const uint32_t addr = rv->X[ir->rs1] + (uint32_t) ir->imm;
947960
if (addr & 3) {
961+
rv->compressed = true;
948962
rv_except_store_misaligned(rv, addr);
949963
return false;
950964
}
@@ -967,6 +981,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
967981
rv->X[1] = rv->PC + ir->insn_len;
968982
rv->PC += ir->imm;
969983
if (rv->PC & 0x1) {
984+
rv->compressed = true;
970985
rv_except_insn_misaligned(rv, rv->PC);
971986
return false;
972987
}
@@ -1044,6 +1059,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
10441059
*/
10451060
rv->PC += ir->imm;
10461061
if (rv->PC & 0x1) {
1062+
rv->compressed = true;
10471063
rv_except_insn_misaligned(rv, rv->PC);
10481064
return false;
10491065
}
@@ -1074,6 +1090,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
10741090
case rv_insn_clwsp: { /* C.LWSP */
10751091
const uint32_t addr = rv->X[rv_reg_sp] + ir->imm;
10761092
if (addr & 3) {
1093+
rv->compressed = true;
10771094
rv_except_load_misaligned(rv, addr);
10781095
return false;
10791096
}
@@ -1088,6 +1105,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
10881105
rv->X[ir->rd] = rv->X[ir->rs2];
10891106
break;
10901107
case rv_insn_cebreak: /* C.EBREAK */
1108+
rv->compressed = true;
10911109
rv->io.on_ebreak(rv);
10921110
/* can branch */
10931111
return true;
@@ -1097,6 +1115,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
10971115
rv->X[rv_reg_ra] = rv->PC + ir->insn_len;
10981116
rv->PC = jump_to;
10991117
if (rv->PC & 0x1) {
1118+
rv->compressed = true;
11001119
rv_except_insn_misaligned(rv, rv->PC);
11011120
return false;
11021121
}
@@ -1116,6 +1135,7 @@ static bool emulate(riscv_t *rv, rv_insn_t *ir)
11161135
case rv_insn_cswsp: { /* C.SWSP */
11171136
const uint32_t addr = rv->X[2] + ir->imm;
11181137
if (addr & 3) {
1138+
rv->compressed = true;
11191139
rv_except_store_misaligned(rv, addr);
11201140
return false;
11211141
}
@@ -1252,6 +1272,7 @@ static void block_translate(riscv_t *rv, block_t *block)
12521272

12531273
/* decode the instruction */
12541274
if (!rv_decode(ir, insn)) {
1275+
rv->compressed = (ir->insn_len == INSN_16);
12551276
rv_except_illegal_insn(rv, insn);
12561277
break;
12571278
}

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