Introduce basic block

This commit introduces the basic block in emulator, meaning that
it makes emulator decode and execute numerous instructions at a
time.

Use queue-based block management to manage the instruction decode
and execution.

In decode stage, allocate a new memory block, put the decoded
instruction into the block, and record the order of instructions by
the member front in struct block_t until the queue is full or the
latest instruction is a branch instruction. The default size of
memory block in queue is 1024.

In execution stage, when the queue is not empty, emulator executes
the memory block that index is rear in struct block_t, frees the
memory block and increments the clock cycle finally.

In particular, when an exception/interrupt occurs, emulator will do
the following steps:
1. Execute the exception/interrupt handler that resets a new program
   counter from the register mtvec and function emulate return false.
2. Enter to the decode stage again, and create new memory blocks based
   on the new program counter.
That is, emulator will dischard old memory blocks and create the new one
from new program counter.

Author: Risheng1128

src/decode.c

@@ -1663,9 +1663,9 @@ static inline bool op_unimp(struct rv_insn_t *rv_insn UNUSED,
 typedef bool (*decode_t)(struct rv_insn_t *rv_insn, uint32_t insn);
 
 /* decode RISC-V instruction */
-bool rv_decode(struct rv_insn_t *ir, uint32_t insn, uint8_t *insn_len)
+bool rv_decode(struct rv_insn_t *ir, uint32_t insn)
 {
-    assert(ir && insn_len);
+    assert(ir);
 
 #define OP_UNIMP op_unimp
 #define OP(insn) op_##insn
@@ -1704,7 +1704,7 @@ bool rv_decode(struct rv_insn_t *ir, uint32_t insn, uint8_t *insn_len)
     if ((insn & FC_OPCODE) != 3) {
         insn &= 0x0000FFFF;
         const uint16_t c_index = (insn & FC_FUNC3) >> 11 | (insn & FC_OPCODE);
-        *insn_len = INSN_16;
+        ir->insn_len = INSN_16;
 
         /* decode instruction (compressed instructions) */
         const decode_t op = rvc_jump_table[c_index];
@@ -1715,7 +1715,7 @@ bool rv_decode(struct rv_insn_t *ir, uint32_t insn, uint8_t *insn_len)
 
     /* standard uncompressed instruction */
     const uint32_t index = (insn & INSN_6_2) >> 2;
-    *insn_len = INSN_32;
+    ir->insn_len = INSN_32;
 
     /* decode instruction */
     const decode_t op = rv_jump_table[index];

src/decode.h

@@ -236,6 +236,19 @@ struct rv_insn_t {
 #if RV32_HAS(EXT_C)
     uint8_t shamt;
 #endif
+
+    /* instruction length */
+    uint8_t insn_len;
+};
+
+/* a translated basic block */
+struct block_t {
+    /* memory blocks */
+    struct rv_insn_t *ir;
+    /* index of memory blocks */
+    uint32_t front, rear;
+    /* maximum of instructions encompased */
+    uint32_t capacity;
 };
 
 /* sign extend a 16 bit value */
@@ -250,7 +263,35 @@ static inline uint32_t sign_extend_b(const uint32_t x)
     return (int32_t) ((int8_t) x);
 }
 
+static inline bool queue_is_full(struct block_t *block)
+{
+    assert(block);
+    return (block->front - block->rear) == block->capacity;
+}
+
+static inline bool queue_is_empty(struct block_t *block)
+{
+    assert(block);
+    return block->front == block->rear;
+}
+
+static inline struct rv_insn_t *get_rear_mem_block(struct block_t *block)
+{
+    assert(block);
+    return block->ir + block->rear;
+}
+
+static inline struct rv_insn_t *alloc_mem_block(struct block_t *block)
+{
+    assert(block);
+    return block->ir + block->front++;
+}
+
+static inline void free_mem_block(struct block_t *block)
+{
+    assert(block);
+    block->rear++;
+}
+
 /* decode the RISC-V instruction */
-bool rv_decode(struct rv_insn_t *rv_insn,
-               const uint32_t insn,
-               uint8_t *insn_len);
+bool rv_decode(struct rv_insn_t *rv_insn, const uint32_t insn);

src/emulate.c

@@ -52,7 +52,8 @@ enum {
 
 static void rv_exception_default_handler(struct riscv_t *rv)
 {
-    rv->csr_mepc += rv->insn_len;
+    struct rv_insn_t *ir = get_rear_mem_block(&rv->block);
+    rv->csr_mepc += ir->insn_len;
     rv->PC = rv->csr_mepc; /* mret */
 }
 
@@ -256,7 +257,7 @@ static bool insn_is_misaligned(uint32_t pc)
     );
 }
 
-static bool rv_emulate(struct riscv_t *rv, struct rv_insn_t *ir)
+static bool emulate(struct riscv_t *rv, struct rv_insn_t *ir)
 {
     switch (ir->opcode) {
     /* RV32I Base Instruction Set */
@@ -286,7 +287,7 @@ static bool rv_emulate(struct riscv_t *rv, struct rv_insn_t *ir)
         rv->PC += ir->imm;
         /* link with return address */
         if (ir->rd)
-            rv->X[ir->rd] = pc + rv->insn_len;
+            rv->X[ir->rd] = pc + ir->insn_len;
         /* check instruction misaligned */
         if (insn_is_misaligned(rv->PC)) {
             rv_except_insn_misaligned(rv, pc);
@@ -308,7 +309,7 @@ static bool rv_emulate(struct riscv_t *rv, struct rv_insn_t *ir)
         rv->PC = (rv->X[ir->rs1] + ir->imm) & ~1U;
         /* link */
         if (ir->rd)
-            rv->X[ir->rd] = pc + rv->insn_len;
+            rv->X[ir->rd] = pc + ir->insn_len;
         /* check instruction misaligned */
         if (insn_is_misaligned(rv->PC)) {
             rv_except_insn_misaligned(rv, pc);
@@ -963,7 +964,7 @@ static bool rv_emulate(struct riscv_t *rv, struct rv_insn_t *ir)
         rv->X[ir->rd] += (int16_t) ir->imm;
         break;
     case rv_insn_cjal:
-        rv->X[1] = rv->PC + rv->insn_len;
+        rv->X[1] = rv->PC + ir->insn_len;
         rv->PC += ir->imm;
         if (rv->PC & 0x1) {
             rv_except_insn_misaligned(rv, rv->PC);
@@ -1055,11 +1056,11 @@ static bool rv_emulate(struct riscv_t *rv, struct rv_insn_t *ir)
          * the value in register rs1' is zero. It expands to beq rs1', x0,
          * offset[8:1].
          */
-        rv->PC += (!rv->X[ir->rs1]) ? (uint32_t) ir->imm : rv->insn_len;
+        rv->PC += (!rv->X[ir->rs1]) ? (uint32_t) ir->imm : ir->insn_len;
         /* can branch */
         return true;
     case rv_insn_cbnez: /* C.BEQZ */
-        rv->PC += (rv->X[ir->rs1]) ? (uint32_t) ir->imm : rv->insn_len;
+        rv->PC += (rv->X[ir->rs1]) ? (uint32_t) ir->imm : ir->insn_len;
         /* can branch */
         return true;
     case rv_insn_cslli: /* C.SLLI */
@@ -1093,7 +1094,7 @@ static bool rv_emulate(struct riscv_t *rv, struct rv_insn_t *ir)
     case rv_insn_cjalr: { /* C.JALR */
         /* Unconditional jump and store PC+2 to ra */
         const int32_t jump_to = rv->X[ir->rs1];
-        rv->X[rv_reg_ra] = rv->PC + rv->insn_len;
+        rv->X[rv_reg_ra] = rv->PC + ir->insn_len;
         rv->PC = jump_to;
         if (rv->PC & 0x1) {
             rv_except_insn_misaligned(rv, rv->PC);
@@ -1125,37 +1126,100 @@ static bool rv_emulate(struct riscv_t *rv, struct rv_insn_t *ir)
     }
 
     /* step over instruction */
-    rv->PC += rv->insn_len;
+    rv->PC += ir->insn_len;
     return true;
 }
 
-void rv_step(struct riscv_t *rv, int32_t cycles)
+static bool emulate_block(struct riscv_t *rv, struct block_t *block)
 {
-    assert(rv);
-    uint32_t insn;
-    struct rv_insn_t ir;
-    const uint64_t cycles_target = rv->csr_cycle + cycles;
-
-    while (rv->csr_cycle < cycles_target && !rv->halt) {
+    /* execute the block */
+    while (!queue_is_empty(block)) {
         /* enforce zero register */
         rv->X[rv_reg_zero] = 0;
 
+        /* execute the instruction */
+        if (!emulate(rv, get_rear_mem_block(&rv->block)))
+            return false;
+
+        free_mem_block(block);
+
+        /* increment the cycles csr */
+        rv->csr_cycle++;
+    }
+    return true;
+}
+
+static bool insn_is_branch(uint8_t opcode)
+{
+    switch (opcode) {
+    case rv_insn_jal:
+    case rv_insn_jalr:
+    case rv_insn_beq:
+    case rv_insn_bne:
+    case rv_insn_blt:
+    case rv_insn_bge:
+    case rv_insn_bltu:
+    case rv_insn_bgeu:
+    case rv_insn_ecall:
+    case rv_insn_ebreak:
+    case rv_insn_mret:
+#if RV32_HAS(EXT_C)
+    case rv_insn_cj:
+    case rv_insn_cjr:
+    case rv_insn_cjal:
+    case rv_insn_cjalr:
+    case rv_insn_cbeqz:
+    case rv_insn_cbnez:
+    case rv_insn_cebreak:
+#endif
+#if RV32_HAS(Zifencei)
+    case rv_insn_fencei:
+#endif
+        return true;
+    }
+    return false;
+}
+
+static void translate_block(struct riscv_t *rv, struct block_t *block)
+{
+    /* translate the basic block */
+    uint32_t pc = rv->PC;
+    block->front = 0;
+    block->rear = 0;
+    while (!queue_is_full(block)) {
+        struct rv_insn_t *ir = alloc_mem_block(block);
+        memset(ir, 0, sizeof(struct rv_insn_t));
+
         /* fetch the next instruction */
-        insn = rv->io.mem_ifetch(rv, rv->PC);
-        memset(&ir, 0, sizeof(struct rv_insn_t));
+        const uint32_t insn = rv->io.mem_ifetch(rv, pc);
 
         /* decode the instruction */
-        if (!rv_decode(&ir, insn, &rv->insn_len)) {
+        if (!rv_decode(ir, insn)) {
             rv_except_illegal_insn(rv, insn);
             break;
         }
 
-        /* execute the instruciton */
-        if (!rv_emulate(rv, &ir))
+        /* stop on branch */
+        if (insn_is_branch(ir->opcode))
             break;
 
-        /* increment the cycles csr */
-        rv->csr_cycle++;
+        /* compute next pc */
+        pc += ir->insn_len;
+    }
+}
+
+void rv_step(struct riscv_t *rv, int32_t cycles)
+{
+    assert(rv);
+    const uint64_t cycles_target = rv->csr_cycle + cycles;
+
+    while (rv->csr_cycle < cycles_target && !rv->halt) {
+        /* translate basic block */
+        translate_block(rv, &rv->block);
+
+        /* execute the block */
+        if (!emulate_block(rv, &rv->block))
+            break;
     }
 }
 
@@ -1201,6 +1265,19 @@ riscv_word_t rv_get_reg(struct riscv_t *rv, uint32_t reg)
     return ~0U;
 }
 
+/* allocate a new code block */
+static bool block_init(struct block_t *block, uint32_t bit)
+{
+    assert(block);
+
+    block->capacity = 1 << bit;
+    block->ir = malloc(sizeof(struct rv_insn_t) * block->capacity);
+    if (!block->ir)
+        return false;
+
+    return true;
+}
+
 struct riscv_t *rv_create(const struct riscv_io_t *io, riscv_user_t userdata)
 {
     assert(io);
@@ -1213,6 +1290,10 @@ struct riscv_t *rv_create(const struct riscv_io_t *io, riscv_user_t userdata)
     /* copy over the userdata */
     rv->userdata = userdata;
 
+    /* place a new block */
+    if (!block_init(&rv->block, 10))
+        return NULL;
+
     /* reset */
     rv_reset(rv, 0U);
 
@@ -1229,9 +1310,16 @@ bool rv_has_halted(struct riscv_t *rv)
     return rv->halt;
 }
 
+static void block_free(struct block_t *block)
+{
+    assert(block);
+    free(block->ir);
+}
+
 void rv_delete(struct riscv_t *rv)
 {
     assert(rv);
+    block_free(&rv->block);
     free(rv);
 }
 
@@ -1242,7 +1330,6 @@ void rv_reset(struct riscv_t *rv, riscv_word_t pc)
 
     /* set the reset address */
     rv->PC = pc;
-    rv->insn_len = INSN_UNKNOWN;
 
     /* set the default stack pointer */
     rv->X[rv_reg_sp] = DEFAULT_STACK_ADDR;

src/riscv_private.h

@@ -10,6 +10,7 @@
 #include "breakpoint.h"
 #include "mini-gdbstub/include/gdbstub.h"
 #endif
+#include "decode.h"
 #include "riscv.h"
 
 #define RV_NUM_REGS 32
@@ -96,6 +97,6 @@ struct riscv_t {
     uint32_t csr_mip;
     uint32_t csr_mbadaddr;
 
-    /* current instruction length */
-    uint8_t insn_len;
+    /* basic block */
+    struct block_t block;
 };