Fix missing barrier in TX_DISABLE for Cortex-R5

This commit fixes thread safety issue in tx_byte_allocate by correcting
clobber list and adding missing compiler fence. This addresses potential
race conditions when aggressive compiler optimization is enabled.

Patched by Pat Kusbel.
See eclipse-threadx#334

Author: jserv

ports/cortex_r5/gnu/inc/tx_port.h

@@ -287,9 +287,9 @@ unsigned int   _tx_thread_interrupt_restore(UINT old_posture);
 #define TX_INTERRUPT_SAVE_AREA                  UINT interrupt_save;
 
 #ifdef TX_ENABLE_FIQ_SUPPORT
-#define TX_DISABLE                              asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) );
+#define TX_DISABLE                              asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) : "memory");
 #else
-#define TX_DISABLE                              asm volatile (" MRS %0,CPSR; CPSID i ": "=r" (interrupt_save) );
+#define TX_DISABLE                              asm volatile (" MRS %0,CPSR; CPSID i ": "=r" (interrupt_save) : "memory");
 #endif
 
 #define TX_RESTORE                              asm volatile (" MSR CPSR_c,%0 "::"r" (interrupt_save) );