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prepare for miri supporting the crc intrinsics
1 parent e8f07df commit 726e389

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Lines changed: 51 additions & 40 deletions

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zlib-rs/src/crc32/acle.rs

Lines changed: 51 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -50,54 +50,65 @@ unsafe fn remainder(mut c: u32, mut buf: &[u8]) -> u32 {
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c
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}
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cfg_select! {
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miri => {
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use core::arch::aarch64::{__crc32b, __crc32h, __crc32d, __crc32w};
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}
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_ => {
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use asm::{__crc32b, __crc32h, __crc32d, __crc32w};
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}
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}
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// FIXME the intrinsics below are stable since rust 1.80.0: remove these and use the standard
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// library versions once our MSRV reaches that version.
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/// CRC32 single round checksum for bytes (8 bits).
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///
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32b)
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#[target_feature(enable = "crc")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
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unsafe fn __crc32b(mut crc: u32, data: u8) -> u32 {
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unsafe {
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core::arch::asm!("crc32b {crc:w}, {crc:w}, {data:w}", crc = inout(reg) crc, data = in(reg) data);
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crc
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mod asm {
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/// CRC32 single round checksum for bytes (8 bits).
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///
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32b)
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#[target_feature(enable = "crc")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
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unsafe fn __crc32b(mut crc: u32, data: u8) -> u32 {
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unsafe {
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core::arch::asm!("crc32b {crc:w}, {crc:w}, {data:w}", crc = inout(reg) crc, data = in(reg) data);
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crc
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}
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}
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}
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/// CRC32 single round checksum for half words (16 bits).
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///
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32h)
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#[target_feature(enable = "crc")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
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unsafe fn __crc32h(mut crc: u32, data: u16) -> u32 {
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unsafe {
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core::arch::asm!("crc32h {crc:w}, {crc:w}, {data:w}", crc = inout(reg) crc, data = in(reg) data);
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crc
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/// CRC32 single round checksum for half words (16 bits).
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///
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32h)
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#[target_feature(enable = "crc")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
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unsafe fn __crc32h(mut crc: u32, data: u16) -> u32 {
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unsafe {
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core::arch::asm!("crc32h {crc:w}, {crc:w}, {data:w}", crc = inout(reg) crc, data = in(reg) data);
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crc
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}
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}
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}
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/// CRC32 single round checksum for words (32 bits).
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///
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32w)
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#[target_feature(enable = "crc")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
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pub unsafe fn __crc32w(mut crc: u32, data: u32) -> u32 {
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unsafe {
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core::arch::asm!("crc32w {crc:w}, {crc:w}, {data:w}", crc = inout(reg) crc, data = in(reg) data);
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crc
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/// CRC32 single round checksum for words (32 bits).
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///
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32w)
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#[target_feature(enable = "crc")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
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pub unsafe fn __crc32w(mut crc: u32, data: u32) -> u32 {
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unsafe {
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core::arch::asm!("crc32w {crc:w}, {crc:w}, {data:w}", crc = inout(reg) crc, data = in(reg) data);
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crc
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}
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}
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}
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/// CRC32 single round checksum for double words (64 bits).
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///
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)
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#[cfg(target_arch = "aarch64")]
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#[target_feature(enable = "crc")]
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unsafe fn __crc32d(mut crc: u32, data: u64) -> u32 {
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unsafe {
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core::arch::asm!("crc32x {crc:w}, {crc:w}, {data:x}", crc = inout(reg) crc, data = in(reg) data);
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crc
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/// CRC32 single round checksum for double words (64 bits).
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///
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)
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#[cfg(target_arch = "aarch64")]
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#[target_feature(enable = "crc")]
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unsafe fn __crc32d(mut crc: u32, data: u64) -> u32 {
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unsafe {
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core::arch::asm!("crc32x {crc:w}, {crc:w}, {data:x}", crc = inout(reg) crc, data = in(reg) data);
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crc
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}
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}
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}
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