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v0.8.1: Improve xRET instruction support (sret, mret, ...).
Add upper 32-bits to cycle counter (for rdtimeh).
1 parent 5614f5c commit 6af9c4b

20 files changed

+112
-70
lines changed

‎src/core/biriscv_alu.v‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
//-----------------------------------------------------------------
22
// biRISC-V CPU
3-
// V0.8.0
3+
// V0.8.1
44
// Ultra-Embedded.com
55
// Copyright 2019-2020
66
//

‎src/core/biriscv_csr.v‎

Lines changed: 12 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
//-----------------------------------------------------------------
22
// biRISC-V CPU
3-
// V0.8.0
3+
// V0.8.1
44
// Ultra-Embedded.com
55
// Copyright 2019-2020
66
//
@@ -87,7 +87,8 @@ module biriscv_csr
8787
//-----------------------------------------------------------------
8888
wire ecall_w = opcode_valid_i && ((opcode_opcode_i & `INST_ECALL_MASK) == `INST_ECALL);
8989
wire ebreak_w = opcode_valid_i && ((opcode_opcode_i & `INST_EBREAK_MASK) == `INST_EBREAK);
90-
wire eret_w = opcode_valid_i && ((opcode_opcode_i & `INST_MRET_MASK) == `INST_MRET);
90+
wire eret_w = opcode_valid_i && ((opcode_opcode_i & `INST_ERET_MASK) == `INST_ERET);
91+
wire [1:0] eret_priv_w = opcode_opcode_i[29:28];
9192
wire csrrw_w = opcode_valid_i && ((opcode_opcode_i & `INST_CSRRW_MASK) == `INST_CSRRW);
9293
wire csrrs_w = opcode_valid_i && ((opcode_opcode_i & `INST_CSRRS_MASK) == `INST_CSRRS);
9394
wire csrrc_w = opcode_valid_i && ((opcode_opcode_i & `INST_CSRRC_MASK) == `INST_CSRRC);
@@ -196,6 +197,9 @@ reg [ 31:0] rd_result_e1_q;
196197
reg [ 31:0] csr_wdata_e1_q;
197198
reg [`EXCEPTION_W-1:0] exception_e1_q;
198199

200+
// Inappropriate xRET for the current exec priv level
201+
wire eret_fault_w = eret_w && (current_priv_w < eret_priv_w);
202+
199203
always @ (posedge clk_i or posedge rst_i)
200204
if (rst_i)
201205
begin
@@ -210,16 +214,19 @@ begin
210214

211215
// Invalid instruction / CSR access fault?
212216
// Record opcode for writing to csr_xtval later.
213-
if (opcode_invalid_i || csr_fault_r)
217+
if (opcode_invalid_i || csr_fault_r || eret_fault_w)
214218
rd_result_e1_q <= opcode_opcode_i;
215219
else
216220
rd_result_e1_q <= csr_rdata_w;
217221

218222
// E1 CSR exceptions
219223
if ((opcode_opcode_i & `INST_ECALL_MASK) == `INST_ECALL)
220224
exception_e1_q <= `EXCEPTION_ECALL + {4'b0, current_priv_w};
221-
else if ((opcode_opcode_i & `INST_MRET_MASK) == `INST_MRET)
222-
exception_e1_q <= `EXCEPTION_ERET; // TODO: MPRIV
225+
// xRET for priv level above this one - fault
226+
else if (eret_fault_w)
227+
exception_e1_q <= `EXCEPTION_ILLEGAL_INSTRUCTION;
228+
else if ((opcode_opcode_i & `INST_ERET_MASK) == `INST_ERET)
229+
exception_e1_q <= `EXCEPTION_ERET_U + {4'b0, eret_priv_w};
223230
else if ((opcode_opcode_i & `INST_EBREAK_MASK) == `INST_EBREAK)
224231
exception_e1_q <= `EXCEPTION_BREAKPOINT;
225232
else if (opcode_invalid_i || csr_fault_r)

‎src/core/biriscv_csr_regfile.v‎

Lines changed: 12 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
//-----------------------------------------------------------------
22
// biRISC-V CPU
3-
// V0.8.0
3+
// V0.8.1
44
// Ultra-Embedded.com
55
// Copyright 2019-2020
66
//
@@ -85,6 +85,7 @@ reg [31:0] csr_mip_q;
8585
reg [31:0] csr_mie_q;
8686
reg [1:0] csr_mpriv_q;
8787
reg [31:0] csr_mcycle_q;
88+
reg [31:0] csr_mcycle_h_q;
8889
reg [31:0] csr_mscratch_q;
8990
reg [31:0] csr_mtval_q;
9091
reg [31:0] csr_mtimecmp_q;
@@ -174,6 +175,7 @@ begin
174175
`CSR_MIE: rdata_r = csr_mie_q & `CSR_MIE_MASK;
175176
`CSR_MCYCLE,
176177
`CSR_MTIME: rdata_r = csr_mcycle_q;
178+
`CSR_MTIMEH: rdata_r = csr_mcycle_h_q;
177179
`CSR_MHARTID: rdata_r = cpu_id_i;
178180
`CSR_MISA: rdata_r = misa_i;
179181
`CSR_MEDELEG: rdata_r = SUPPORT_SUPER ? (csr_medeleg_q & `CSR_MEDELEG_MASK) : 32'b0;
@@ -314,11 +316,10 @@ begin
314316
end
315317
end
316318
// Exception return
317-
else if (exception_i == `EXCEPTION_ERET)
319+
else if (exception_i >= `EXCEPTION_ERET_U && exception_i <= `EXCEPTION_ERET_M)
318320
begin
319-
// TODO: Not quite correct - should check which ERET insn
320321
// MRET (return from machine)
321-
if (csr_mpriv_q == `PRIV_MACHINE)
322+
if (exception_i[1:0] == `PRIV_MACHINE)
322323
begin
323324
// Set privilege level to previous MPP
324325
csr_mpriv_r = csr_sr_r[`SR_MPP_R];
@@ -490,6 +491,7 @@ begin
490491
csr_mie_q <= 32'b0;
491492
csr_mpriv_q <= `PRIV_MACHINE;
492493
csr_mcycle_q <= 32'b0;
494+
csr_mcycle_h_q <= 32'b0;
493495
csr_mscratch_q <= 32'b0;
494496
csr_mtimecmp_q <= 32'b0;
495497
csr_mtime_ie_q <= 1'b0;
@@ -534,6 +536,10 @@ begin
534536

535537
csr_mip_next_q <= buffer_mip_w ? csr_mip_next_r : 32'b0;
536538

539+
// Increment upper cycle counter on lower 32-bit overflow
540+
if (csr_mcycle_q == 32'hFFFFFFFF)
541+
csr_mcycle_h_q <= csr_mcycle_h_q + 32'd1;
542+
537543
`ifdef HAS_SIM_CTRL
538544
// CSR SIM_CTRL (or DSCRATCH)
539545
if ((csr_waddr_i == `CSR_DSCRATCH || csr_waddr_i == `CSR_SIM_CTRL) && ~(|exception_i))
@@ -572,11 +578,10 @@ begin
572578
branch_target_r = (irq_priv_q == `PRIV_MACHINE) ? csr_mtvec_q : csr_stvec_q;
573579
end
574580
// Exception return
575-
else if (exception_i == `EXCEPTION_ERET)
581+
else if (exception_i >= `EXCEPTION_ERET_U && exception_i <= `EXCEPTION_ERET_M)
576582
begin
577-
// TODO: Not quite correct - should check which ERET insn
578583
// MRET (return from machine)
579-
if (csr_mpriv_q == `PRIV_MACHINE)
584+
if (exception_i[1:0] == `PRIV_MACHINE)
580585
begin
581586
branch_r = 1'b1;
582587
branch_target_r = csr_mepc_q;

‎src/core/biriscv_decode.v‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
//-----------------------------------------------------------------
22
// biRISC-V CPU
3-
// V0.8.0
3+
// V0.8.1
44
// Ultra-Embedded.com
55
// Copyright 2019-2020
66
//

‎src/core/biriscv_decoder.v‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
//-----------------------------------------------------------------
22
// biRISC-V CPU
3-
// V0.8.0
3+
// V0.8.1
44
// Ultra-Embedded.com
55
// Copyright 2019-2020
66
//
@@ -83,7 +83,7 @@ wire invalid_w = valid_i &&
8383
((opcode_i & `INST_SW_MASK) == `INST_SW) ||
8484
((opcode_i & `INST_ECALL_MASK) == `INST_ECALL) ||
8585
((opcode_i & `INST_EBREAK_MASK) == `INST_EBREAK) ||
86-
((opcode_i & `INST_MRET_MASK) == `INST_MRET) ||
86+
((opcode_i & `INST_ERET_MASK) == `INST_ERET) ||
8787
((opcode_i & `INST_CSRRW_MASK) == `INST_CSRRW) ||
8888
((opcode_i & `INST_CSRRS_MASK) == `INST_CSRRS) ||
8989
((opcode_i & `INST_CSRRC_MASK) == `INST_CSRRC) ||
@@ -204,7 +204,7 @@ assign div_o = enable_muldiv_i &&
204204

205205
assign csr_o = ((opcode_i & `INST_ECALL_MASK) == `INST_ECALL) ||
206206
((opcode_i & `INST_EBREAK_MASK) == `INST_EBREAK) ||
207-
((opcode_i & `INST_MRET_MASK) == `INST_MRET) ||
207+
((opcode_i & `INST_ERET_MASK) == `INST_ERET) ||
208208
((opcode_i & `INST_CSRRW_MASK) == `INST_CSRRW) ||
209209
((opcode_i & `INST_CSRRS_MASK) == `INST_CSRRS) ||
210210
((opcode_i & `INST_CSRRC_MASK) == `INST_CSRRC) ||

‎src/core/biriscv_defs.v‎

Lines changed: 9 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
//-----------------------------------------------------------------
22
// biRISC-V CPU
3-
// V0.8.0
3+
// V0.8.1
44
// Ultra-Embedded.com
55
// Copyright 2019-2020
66
//
@@ -200,10 +200,9 @@
200200
`define INST_EBREAK 32'h100073
201201
`define INST_EBREAK_MASK 32'hffffffff
202202

203-
// mret / sret
204-
`define INST_MRET 32'h10200073
205-
`define INST_MRET_MASK 32'hdfffffff
206-
`define INST_MRET_R 29
203+
// eret
204+
`define INST_ERET 32'h200073
205+
`define INST_ERET_MASK 32'hcfffffff
207206

208207
// csrrw
209208
`define INST_CSRRW 32'h1073
@@ -485,8 +484,11 @@
485484
`define EXCEPTION_PAGE_FAULT_STORE 6'h1f
486485
`define EXCEPTION_EXCEPTION 6'h10
487486
`define EXCEPTION_INTERRUPT 6'h20
488-
`define EXCEPTION_ERET 6'h30
489-
`define EXCEPTION_FENCE 6'h31
487+
`define EXCEPTION_ERET_U 6'h30
488+
`define EXCEPTION_ERET_S 6'h31
489+
`define EXCEPTION_ERET_H 6'h32
490+
`define EXCEPTION_ERET_M 6'h33
491+
`define EXCEPTION_FENCE 6'h34
490492
`define EXCEPTION_TYPE_MASK 6'h30
491493
`define EXCEPTION_SUBTYPE_R 3:0
492494

‎src/core/biriscv_divider.v‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
//-----------------------------------------------------------------
22
// biRISC-V CPU
3-
// V0.8.0
3+
// V0.8.1
44
// Ultra-Embedded.com
55
// Copyright 2019-2020
66
//

‎src/core/biriscv_exec.v‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
//-----------------------------------------------------------------
22
// biRISC-V CPU
3-
// V0.8.0
3+
// V0.8.1
44
// Ultra-Embedded.com
55
// Copyright 2019-2020
66
//

‎src/core/biriscv_fetch.v‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
//-----------------------------------------------------------------
22
// biRISC-V CPU
3-
// V0.8.0
3+
// V0.8.1
44
// Ultra-Embedded.com
55
// Copyright 2019-2020
66
//

‎src/core/biriscv_frontend.v‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
//-----------------------------------------------------------------
22
// biRISC-V CPU
3-
// V0.8.0
3+
// V0.8.1
44
// Ultra-Embedded.com
55
// Copyright 2019-2020
66
//
@@ -118,16 +118,16 @@ wire fetch_pc_accept_w;
118118

119119
biriscv_npc
120120
#(
121-
.SUPPORT_BRANCH_PREDICTION(SUPPORT_BRANCH_PREDICTION)
122-
,.NUM_BTB_ENTRIES(NUM_BTB_ENTRIES)
121+
.NUM_BTB_ENTRIES(NUM_BTB_ENTRIES)
122+
,.SUPPORT_BRANCH_PREDICTION(SUPPORT_BRANCH_PREDICTION)
123+
,.GSHARE_ENABLE(GSHARE_ENABLE)
124+
,.NUM_RAS_ENTRIES_W(NUM_RAS_ENTRIES_W)
125+
,.NUM_BHT_ENTRIES_W(NUM_BHT_ENTRIES_W)
126+
,.BHT_ENABLE(BHT_ENABLE)
123127
,.NUM_BTB_ENTRIES_W(NUM_BTB_ENTRIES_W)
124128
,.NUM_BHT_ENTRIES(NUM_BHT_ENTRIES)
125-
,.NUM_BHT_ENTRIES_W(NUM_BHT_ENTRIES_W)
126129
,.RAS_ENABLE(RAS_ENABLE)
127-
,.GSHARE_ENABLE(GSHARE_ENABLE)
128-
,.BHT_ENABLE(BHT_ENABLE)
129130
,.NUM_RAS_ENTRIES(NUM_RAS_ENTRIES)
130-
,.NUM_RAS_ENTRIES_W(NUM_RAS_ENTRIES_W)
131131
)
132132
u_npc
133133
(
@@ -154,8 +154,8 @@ u_npc
154154

155155
biriscv_decode
156156
#(
157-
.SUPPORT_MULDIV(SUPPORT_MULDIV)
158-
,.EXTRA_DECODE_STAGE(EXTRA_DECODE_STAGE)
157+
.EXTRA_DECODE_STAGE(EXTRA_DECODE_STAGE)
158+
,.SUPPORT_MULDIV(SUPPORT_MULDIV)
159159
)
160160
u_decode
161161
(

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