Processor [AMD Ryzen 9 9950X3D 16-Core Processor] |- Architecture [Zen5/Granite Ridge] |- Vendor ID [AuthenticAMD] |- Microcode [0x0b404023] |- Signature [ BF_44] |- Stepping [ 0] |- Online CPU [ 32/ 32] |- Base Clock [100.000] |- Frequency (MHz) Ratio Min 3000.01 < 30 > Max 4300.02 < 43 > |- Factory [100.000] 4300 [ 43 ] |- Performance TGT 4300.02 < 43 > |- CPPC Min 3700.02 < 37 > Max 2800.01 < 28 > TGT AUTO < 0 > |- Boost [ UNLOCK] XFR 5700.03 [ 57 ] CPB 5700.03 [ 57 ] |- P-State P1 3000.01 < 30 > |- Uncore [ LOCK] CLK 1500.01 [ 15 ] MEM 3000.01 [ 30 ] Instruction Set Extensions |- 3DNow!/Ext [N/N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y] |- AVX512-F [Y] AVX512-DQ [Y] AVX512-IFMA [Y] AVX512-PF [N] |- AVX512-ER [N] AVX512-CD [Y] AVX512-BW [Y] AVX512-VL [Y] |- AVX512-VBMI [Y] AVX512-VBMI2 [Y] AVX512-VNNI [Y] AVX512-ALG [Y] |- AVX512-VPOP [Y] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [Y] |- AVX512-BF16 [Y] AVX-VNNI-VEX [Y] AVX-FP128 [N] AVX-FP256 [N] |- BMI1/BMI2 [Y/Y] CLWB [Y] CLFLUSH [Y] CLFLUSH-OPT [Y] |- CLAC-STAC [Y] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y] |- F16C [Y] FPU [Y] FXSR [Y] LAHF-SAHF [Y] |- MMX/Ext [Y/Y] MON/MWAITX [Y/Y] MOVBE [Y] PCLMULQDQ [Y] |- POPCNT [Y] RDRAND [Y] RDSEED [Y] RDTSCP [Y] |- SEP [Y] SHA [Y] SSE [Y] SSE2 [Y] |- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/Y] SSE4.2 [Y] |- SERIALIZE [N] SYSCALL [Y] RDPID [Y] UMIP [Y] |- VAES [Y] VPCLMULQDQ [Y] PREFETCH/W [Y] LZCNT [Y] Features |- 1 GB Pages Support 1GB-PAGES [Capable] |- 100 MHz multiplier Control 100MHzSteps [Missing] |- Advanced Configuration & Power Interface ACPI [Capable] |- Advanced Programmable Interrupt Controller APIC [Capable] |- Advanced Virtual Interrupt Controller AVIC [Capable] |- APIC Timer Invariance ARAT [Capable] |- LOCK prefix to read CR8 AltMov [Capable] |- Clear Zero Instruction CLZERO [Capable] |- Core Multi-Processing CMP Legacy [Capable] |- L1 Data Cache Context ID CNXT-ID [Missing] |- Collaborative Processor Performance Control CPPC [Capable] |- Direct Cache Access DCA [Missing] |- Debugging Extension DE [Capable] |- Debug Store & Precise Event Based Sampling DS, PEBS [Missing] |- CPL Qualified Debug Store DS-CPL [Missing] |- 64-Bit Debug Store DTES64 [Missing] |- Fast Short REP CMPSB|SCASB FSRC [Capable] |- Fast Short REP MOVSB FSRM [Capable] |- Fast Short REP STOSB FSRS [Capable] |- Fast-String Operation ERMS [Capable] |- Fused Multiply Add FMA4 [Missing] |- Fused Multiply Add FMA [Capable] |- Hardware Lock Elision HLE [Missing] |- Hyper-Threading Technology HTT [Capable] |- Hardware P-state control HwP [Capable] |- Instruction Based Sampling IBS [Capable] |- Instruction INVLPGB INVLPGB [Missing] |- Instruction INVPCID INVPCID [Capable] |- Long Mode 64 bits IA64 | LM [Capable] |- LightWeight Profiling LWP [Missing] |- Memory Bandwidth Enforcement MBE [Capable] |- Machine-Check Architecture MCA [Capable] |- Instruction MCOMMIT MCOMMIT [Missing] |- Model Specific Registers MSR [Capable] |- Memory Type Range Registers MTRR [Capable] |- No-Execute Page Protection NX [Capable] |- OS-Enabled Ext. State Management OSXSAVE [Capable] |- OS Visible Work-around OSVW [Capable] |- Physical Address Extension PAE [Capable] |- Page Attribute Table PAT [Capable] |- Pending Break Enable PBE [Missing] |- Process Context Identifiers PCID [Missing] |- Perfmon and Debug Capability PDCM [Missing] |- Page Global Enable PGE [Capable] |- Page Size Extension PSE [Capable] |- 36-bit Page Size Extension PSE36 [Capable] |- Processor Serial Number PSN [Missing] |- PREFETCHIT0/1 Instructions PREFETCHI [Capable] |- Resource Director Technology/PQE RDT-A [Capable] |- Resource Director Technology/PQM RDT-M [Capable] |- Read Processor Register at User level RDPRU [Capable] |- Restricted Transactional Memory RTM [Missing] |- Safer Mode Extensions SMX [Missing] |- Self-Snoop SS [Missing] |- Supervisor-Mode Access Prevention SMAP [Capable] |- Supervisor-Mode Execution Prevention SMEP [Capable] |- Trailing Bit Manipulation TBM [Missing] |- Translation Cache Extension TCE [Capable] |- Time Stamp Counter TSC [Invariant] |- Time Stamp Counter Deadline TSC-DEADLINE [Missing] |- TSX Force Abort MSR Register TSX-ABORT [Missing] |- TSX Suspend Load Address Tracking TSX-LDTRK [Missing] |- User-Mode Instruction Prevention UMIP [Capable] |- Virtual Mode Extension VME [Capable] |- Virtual Machine Extensions VMX [Missing] |- Write Back & Do Not Invalidate Cache WBNOINVD [Capable] |- Extended xAPIC Support x2APIC [ xAPIC] |- AVIC controller for x2APIC x2AVIC [Capable] |- XSAVE/XSTOR States XSAVE [Capable] |- xTPR Update Control xTPR [Missing] |- Extended Operation Support XOP [Missing] Mitigation mechanisms |- Indirect Branch Restricted Speculation IBRS [Capable] |- IBRS Always-On preferred by processor [ Unable] |- IBRS preferred over software solution [Capable] |- IBRS provides same speculation limits [Capable] |- Indirect Branch Prediction Barrier IBPB [Capable] |- Selective Branch Predictor Barrier SBPB [Capable] |- Single Thread Indirect Branch Predictor STIBP [ Enable] |- Speculative Store Bypass Disable SSBD [Capable] |- SSBD use VIRT_SPEC_CTRL register [ Unable] |- SSBD not needed on this processor [ Unable] |- No Speculative Return Stack Overflow SRSO_NO [ Unable] |- No SRSO at the User-Kernel boundary [Capable] |- No Branch Type Confusion BTC_NO [Capable] |- BTC on Non-Branch instruction BTC-NOBR [ Unable] |- Limited Early Redirect Window AGENPICK [ Unable] |- Arch - No Fast Predictive Store Forwarding PSFD [Capable] |- Arch - Enhanced Predictive Store Forwarding EPSF [Capable] |- Arch - Cross Processor Information Leak XPROC_LEAK [ Unable] Security Features |- CET Shadow Stack features CET-SS [Capable] |- Secure Init and Jump with Attestation SKINIT [Capable] |- Secure Encrypted Virtualization SEV [Missing] |- SEV - Encrypted State SEV-ES [Missing] |- SEV - Secure Nested Paging SEV-SNP [Missing] |- Guest Mode Execute Trap GMET [Capable] |- Supervisor Shadow Stack SSS [Capable] |- VM Permission Levels VMPL [Missing] |- VMPL Supervisor Shadow Stack VMPL-SSS [Missing] |- Secure Memory Encryption SME [Capable] |- Transparent SME TSME [ Enable] |- Secure Multi-Key Memory Encryption SME-MK [Missing] |- DRAM Data Scrambling Scrambler [ Enable] Technologies |- Instruction Cache Unit |- L1 IP Prefetcher L1 HW IP < ON> |- Data Cache Unit |- L1 Prefetcher L1 HW < ON> |- Cache Prefetchers |- L2 Prefetcher L2 HW < ON> |- L1 Stride Prefetcher L1 Stride < ON> |- L1 Region Prefetcher L1 Region < ON> |- L1 Burst Prefetch Mode L1 Burst < ON> |- L2 Stream HW Prefetcher L2 Stream < ON> |- L2 Up/Down Prefetcher L2 Up/Down < ON> |- System Management Mode SMM-Lock [ ON] |- Simultaneous Multithreading SMT [ ON] |- PowerNow! CnQ [ ON] |- Core C-States CCx [ ON] |- Core Performance Boost CPB < ON> |- Watchdog Timer WDT < ON> |- Virtualization SVM [ ON] |- I/O MMU AMD-V [ ON] |- Version [ 0.1] |- Hypervisor [OFF] |- Vendor ID [ N/A] Performance Monitoring |- Version PM [ 2] |- Counters: General Fixed | { 6, 6, 16 } x 48 bits 3 x 64 bits |- Enhanced Halt State C1E |- C2 UnDemotion C2U < ON> |- C3 UnDemotion C3U < ON> |- Core C6 State CC6 < ON> |- Package C6 State PC6 < ON> |- Legacy Frequency ID control FID [OFF] |- Legacy Voltage ID control VID [OFF] |- P-State Hardware Coordination Feedback MPERF/APERF [ ON] |- Core C-States |- C-States Base Address BAR [ 0x413 ] |- ACPI Processor C-States _CST [ 3] |- MONITOR/MWAIT |- State index: #0 #1 #2 #3 #4 #5 #6 #7 |- Sub C-State: 1 2 0 0 0 0 0 0 |- Monitor-Mwait Extensions EMX [Capable] |- Interrupt Break-Event IBE [Capable] |- Core Cycles [Capable] |- Instructions Retired [Capable] |- Reference Cycles [Capable] |- Last Level Cache References [Capable] |- Global Time Stamp Counter [Missing] |- Data Fabric Performance Counter [Capable] |- Core Performance Counter [Capable] |- Processor Performance Control _PCT [ Enable] |- Performance Supported States _PSS [ 2] |- Performance Present Capabilities _PPC [ 0] |- Continuous Performance Control _CPC [Missing] Power, Current & Thermal |- Temperature Offset:Junction TjMax [ 49: 95 C] |- CPPC Energy Preference EPP < 0> |- Digital Thermal Sensor DTS [Capable] |- Power Limit Notification PLN [Missing] |- Package Thermal Management PTM [Missing] |- Thermal Monitor 1 TTP [ Enable] |- Thermal Monitor 2 HTC [ Enable] |- Thermal Design Power TDP [Missing] |- Minimum Power Min [Missing] |- Maximum Power Max [Missing] |- Thermal Design Power Package [Disable] |- Power Limit PL1 [ 0 W] |- Time Window TW1 [ 0 ns] |- Power Limit PL2 [ 0 W] |- Time Window TW2 [ 0 ns] |- Thermal Design Power Core [Disable] |- Power Limit PL1 [ 0 W] |- Time Window TW1 [ 0 ns] |- Thermal Design Power Uncore [Disable] |- Power Limit PL1 [ 0 W] |- Time Window TW1 [ 0 ns] |- Thermal Design Power DRAM [Disable] |- Power Limit PL1 [ 0 W] |- Time Window TW1 [ 0 ns] |- Thermal Design Power Platform [Disable] |- Power Limit PL1 [ 0 W] |- Time Window TW1 [ 0 ns] |- Power Limit PL2 [ 0 W] |- Time Window TW2 [ 0 ns] |- Package Power Tracking PPT [Missing] |- Electrical Design Current EDC [Missing] |- Thermal Design Current TDC [Missing] |- Core Thermal Point |- Package Thermal Point |- Thermal Monitor Trip Limit [ 115 C] |- HTC Temperature Limit Limit [ 127 C] |- HTC Temperature Hysteresis Threshold [ 2 C] |- Units |- Power watt [ Missing] |- Energy joule [ 0.000015259] |- Window second [ 0.000976562]