diff --git a/arch/arm64/boot/dts/hi6220.dtsi b/arch/arm64/boot/dts/hi6220.dtsi index 2f7f8a141a5dab..763a5816d272c7 100644 --- a/arch/arm64/boot/dts/hi6220.dtsi +++ b/arch/arm64/boot/dts/hi6220.dtsi @@ -692,6 +692,7 @@ <0x0 0xf4410000 0x0 0x1000>; reg-names = "ade_base", "media_base"; + interrupts = <0 114 0x4>; clocks = <&clock_media HI6220_ADE_CORE>, <&clock_media HI6220_CODEC_JPEG>, <&clock_media HI6220_ADE_PIX_SRC>, diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index a41742c9012599..86da8bcc0a7b23 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -381,3 +381,7 @@ CONFIG_USB_SERIAL_FTDI_SIO=m CONFIG_COMPAT_BINFMT_ELF=y CONFIG_COMPAT=y CONFIG_SYSVIPC_COMPAT=y + +CONFIG_ION_HISI=y +CONFIG_ION=y +CONFIG_ANDROID=y diff --git a/drivers/gpu/drm/hisilicon/Makefile b/drivers/gpu/drm/hisilicon/Makefile index ee3834eb7fe9df..01439a6fcd21c8 100644 --- a/drivers/gpu/drm/hisilicon/Makefile +++ b/drivers/gpu/drm/hisilicon/Makefile @@ -1,8 +1,10 @@ +ccflags-y += -I$(srctree)/drivers/staging/android hisi-drm-y := hisi_drm_drv.o \ hisi_drm_ade.o \ hisi_drm_dsi.o \ hisi_drm_fb.o \ - hisi_mipi_reg.o + hisi_mipi_reg.o \ + hisi_ade_cmdqueue.o obj-$(CONFIG_DRM_HISI) += hisi-drm.o obj-$(CONFIG_DRM_HISI_FBDEV) += hisi_drm_fbdev.o diff --git a/drivers/gpu/drm/hisilicon/hisi_ade_cmdqueue.c b/drivers/gpu/drm/hisilicon/hisi_ade_cmdqueue.c new file mode 100644 index 00000000000000..7d8038c4844041 --- /dev/null +++ b/drivers/gpu/drm/hisilicon/hisi_ade_cmdqueue.c @@ -0,0 +1,145 @@ +/* Copyright (c) 2008-2010, Hisilicon Tech. Co., Ltd. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include +#include "hisi_ade_cmdqueue.h" +#include + +#define ADE_INVAL_REG (0xffff) + +struct write_cmd_head wr_cmd; + +/* BOARD TYPE */ +enum { + ASIC_BOARD = 0, + SFT_BOARD = 1, +}; + +/********** ADE Register Union Struct ***********/ +// Define the union U_RD_CH1_PE +union U_RD_CH1_PE { + // Define the struct bits + struct + { + unsigned int rd_ch1_qos : 4 ; // [3..0] + unsigned int rd_ch1_qos_sec : 4 ; // [7..4] + unsigned int rd_ch1_qos_thd : 4 ; // [11..8] + unsigned int rd_ch1_qos_cfg : 1 ; // [12] + unsigned int Reserved_77 : 11 ; // [23..13] + unsigned int rd_ch1_min_burst_len : 4 ; // [27..24] + unsigned int Reserved_76 : 4 ; // [31..28] + } bits; + + // Define an unsigned member + unsigned int u32; + +} ; + +void ade_cmdq_wr_eof_cmd(void *cmdbuff_vaddr, u32 *cmd_len) +{ + NULL_EOF_CMD eof_cmd; + NULL_EOF_CMD null_cmd; + u32 align_count = 0; + unsigned i = 0; + + eof_cmd.ul32 = 0; + eof_cmd.bits.cmd_type = ADE_CMD_TYPE_EOF; + + null_cmd.ul32 = 0; + null_cmd.bits.cmd_type = ADE_CMD_TYPE_NULL; + + align_count = (*cmd_len + sizeof(eof_cmd.ul32)) % ADE_CMD_ALIGN_BYTE_LEN ; + if (align_count != 0) { + /* align up to 16*4 byte */ + align_count = (((*cmd_len / ADE_CMD_ALIGN_BYTE_LEN + 1) * ADE_CMD_ALIGN_BYTE_LEN) - sizeof(eof_cmd.ul32) - *cmd_len) / 4; + for (i = 0; i < align_count; i++) { + memcpy((char*)cmdbuff_vaddr + *cmd_len, &null_cmd, sizeof(null_cmd.ul32)); + *cmd_len += sizeof(null_cmd.ul32); + } + } + + memcpy((char*)cmdbuff_vaddr + *cmd_len, &eof_cmd.ul32, sizeof(eof_cmd.ul32)); + *cmd_len += sizeof(eof_cmd.ul32); + +} + +void ade_cmdq_wr_cmd2buff(void* cmdbuff_vaddr, u32 *cmd_len) +{ + u32 wr_cmd_len = 0; + + if (wr_cmd.cmd_head.bits.first_reg_offset == ADE_INVAL_REG) { + return; + } + + wr_cmd_len = sizeof(wr_cmd.cmd_head.ul32) * (wr_cmd.cmd_head.bits.arg_len + 1); + wr_cmd.cmd_head.bits.arg_len -= 1; + + memcpy((char*)cmdbuff_vaddr + *cmd_len, &wr_cmd, wr_cmd_len); + *cmd_len += wr_cmd_len; + + wr_cmd.cmd_head.bits.cmd_type = ADE_CMD_TYPE_WRITE; + wr_cmd.cmd_head.bits.arg_len = 0; + wr_cmd.cmd_head.bits.first_reg_offset = ADE_INVAL_REG; +} + +/************************* RDMA *********************************/ +inline void ade_cmdq_wr_cmd(u32 reg_addr, u32 val) +{ + u32 last_reg; + + if (reg_addr == ADE_INVAL_REG) { + return; + } + + last_reg = wr_cmd.cmd_head.bits.arg_len * 4 + wr_cmd.cmd_head.bits.first_reg_offset; + + wr_cmd.cmd_head.bits.cmd_type = ADE_CMD_TYPE_WRITE; + if ((last_reg == reg_addr) && (wr_cmd.cmd_head.bits.arg_len < ADE_CMD_WITE_REG_MAX)) { + wr_cmd.reg_val[wr_cmd.cmd_head.bits.arg_len] = val; + wr_cmd.cmd_head.bits.arg_len++; + } else { + wr_cmd.cmd_head.bits.first_reg_offset = reg_addr; + wr_cmd.cmd_head.bits.arg_len = 1; + wr_cmd.reg_val[0] = val; + } +} + +void ade_cmdq_wr_rdma_pe_cmd(u32 reg_addr, u32 ch_type, u32 rotation) +{ + volatile union U_RD_CH1_PE rdma_pe; + + rdma_pe.u32 = 0; + + /* the min burst len is 16 when no rotation, is 4 when have online rotation */ + rdma_pe.bits.rd_ch1_min_burst_len = 0xf; + if (OVERLAY_PIPE_TYPE_ONLINE == ch_type) { + rdma_pe.bits.rd_ch1_qos = 4; + if (rotation != ADE_ROT_NOP) { + rdma_pe.bits.rd_ch1_min_burst_len = 0x3; + } + } else { + rdma_pe.bits.rd_ch1_qos = 2; + } +#if 0 + if (SFT_BOARD == fb_get_board_type()) { + rdma_pe.bits.rd_ch1_min_burst_len = 0x3; + } +#endif + ade_cmdq_wr_cmd(reg_addr, rdma_pe.u32); + +} diff --git a/drivers/gpu/drm/hisilicon/hisi_ade_cmdqueue.h b/drivers/gpu/drm/hisilicon/hisi_ade_cmdqueue.h new file mode 100644 index 00000000000000..fe73ca67b0c2c3 --- /dev/null +++ b/drivers/gpu/drm/hisilicon/hisi_ade_cmdqueue.h @@ -0,0 +1,102 @@ +/* Copyright (c) 2008-2011, Hisilicon Tech. Co., Ltd. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __ADE_CMDQUEUE_H__ +#define __ADE_CMDQUEUE_H__ + +#define ADE_CMD_WITE_REG_MAX (128) +#define ADE_CMD_ALIGN_BYTE_LEN (64) /* 16 * 4, 16 words */ +/*************************enum***************************/ +enum { + ADE_CMD_TYPE_NULL = 0x0, + ADE_CMD_TYPE_WRITE = 0x1, + ADE_CMD_TYPE_READ = 0x2, + ADE_CMD_TYPE_WAIT = 0x3, + ADE_CMD_TYPE_EOF = 0x4, + ADE_CMD_TYPE_INVAL +}; + +enum ADE_ROT{ + ADE_ROT_NOP = 0, + ADE_ROT_90, + ADE_ROT_180, + ADE_ROT_270, + ADE_ROT_H_MIRROR, + ADE_ROT_V_MIRROR, + ADE_ROT_90_H_MIRROR, + ADE_ROT_90_V_MIRROR, + ADE_ROT_INVALID +}; +enum OVERLAY_PIPE_NUM{ + OVERLAY_PIPE_ADE_CH1 = 0, + OVERLAY_PIPE_ADE_CH2, + OVERLAY_PIPE_ADE_CH3, + OVERLAY_PIPE_ADE_CH4, + OVERLAY_PIPE_ADE_CH5, + OVERLAY_PIPE_ADE_CH6, + OVERLAY_PIPE_ADE_DISP, + + OVERLAY_PIPE_ADE_MAX +}; + +enum OVERLAY_PIPE_TYPE { + OVERLAY_PIPE_TYPE_ONLINE = 0, + OVERLAY_PIPE_TYPE_OFFLINE, + OVERLAY_PIPE_TYPE_COPYBIT, + OVERLAY_PIPE_TYPE_DISPLAY, + OVERLAY_PIPE_TYPE_INVAL +}; + +typedef union { + struct { + u32 first_reg_offset : 16; + u32 arg_len : 8; + u32 cmd_type : 8; + }bits; + u32 ul32; +}WRITE_CMD_HEAD; + +typedef union { + struct { + u32 reserved : 24; + u32 cmd_type : 8; + }bits; + u32 ul32; +}NULL_EOF_CMD; + +struct write_cmd_head { + WRITE_CMD_HEAD cmd_head; + u32 reg_val[ADE_CMD_WITE_REG_MAX]; + }; + +extern void ade_cmdq_wr_rdma_pe_cmd(u32 reg_addr, u32 ch_type, u32 rotation); +extern void ade_cmdq_wr_cmd(u32 reg_addr, u32 val); +extern void ade_cmdq_wr_cmd2buff(void *cmdbuff_vaddr, u32 *cmd_len); +extern void ade_cmdq_wr_eof_cmd(void *cmdbuff_vaddr, u32 *cmd_len); +#endif /* ADE_CMDQUEUE_H */ diff --git a/drivers/gpu/drm/hisilicon/hisi_ade_reg.h b/drivers/gpu/drm/hisilicon/hisi_ade_reg.h index 95eb9d18020e79..76cd19be80960f 100644 --- a/drivers/gpu/drm/hisilicon/hisi_ade_reg.h +++ b/drivers/gpu/drm/hisilicon/hisi_ade_reg.h @@ -13,6 +13,8 @@ #ifndef __HISI_ADE_REG_H__ #define __HISI_ADE_REG_H__ +#include "hisi_ade_cmdqueue.h" + /********** ADE Register Offset ***********/ #define ADE_CTRL_REG (0x4) #define ADE_CTRL1_REG (0x8C) @@ -27,8 +29,10 @@ #define ADE_OVLY1_TRANS_CFG_REG (0x2C) #define ADE_CTRAN5_TRANS_CFG_REG (0x40) #define ADE_EN_REG (0x100) -#define INTR_MASK_CPU_0_REG (0xC10) -#define INTR_MASK_CPU_1_REG (0xC14) +#define INTR_MASK_CPU0_REG (0xC10) +#define INTR_MASK_CPU1_REG (0xC14) +#define INTR_MASK_STATE_CPU1_REG (0xC0C) +#define INTR_CLEAR_CPU1_REG (0xC1C) #define ADE_FRM_DISGARD_CTRL_REG (0xA4) #define ADE_SOFT_RST_SEL0_REG (0x78) #define ADE_SOFT_RST_SEL1_REG (0x7C) @@ -47,17 +51,113 @@ #define ADE_CTRAN6_DIS_REG (0x5504) #define ADE_CTRAN6_IMAGE_SIZE_REG (0x553C) #define ADE_CTRAN6_CFG_OK_REG (0x5540) +#define ADE_DMA_AXI_MUX_REG (0x50) +#define RD_CH_DISP_PE_REG (0x1400) +#define RD_CH_CMDQ1_PE_REG (0x1500) +#define RD_CH_CMDQ1_CTRL_REG (0x1504) +#define RD_CH_CMDQ1_ADDR_REG (0x1508) +#define RD_CH_CMDQ1_LEN_REG (0x150C) +#define RD_CH_CMDQ1_EN_REG (0x1510) +#define RD_CH_CMDQ2_PE_REG (0x1580) +#define RD_CH_CMDQ2_CTRL_REG (0x1584) +#define RD_CH_CMDQ2_ADDR_REG (0x1588) +#define RD_CH_CMDQ2_LEN_REG (0x158C) +#define RD_CH_CMDQ2_EN_REG (0x1590) + +enum { + ADE_ISR1_CMDQ1_CMPL = 0x200, + ADE_ISR1_CMDQ2_CMPL = 0x400, + ADE_ISR1_CMDQ1_ERR_CMD = 0x1000, + ADE_ISR1_CMDQ2_ERR_CMD = 0x2000, + ADE_ISR1_CMDQ1_WAIT_TIMER_OUT = 0x8000, + ADE_ISR1_CMDQ2_WAIT_TIMER_OUT = 0x10000, + ADE_ISR1_CMDQ1_RD_WR_TIMER_OUT = 0x40000, + ADE_ISR1_CMDQ2_RD_WR_TIMER_OUT = 0x80000, + ADE_ISR1_OVLY1_CMPL = 0x00200000, + ADE_ISR1_RES_SWITCH_CMPL = 0x80000000 +}; -/********** ADE Register Union Struct ***********/ union U_ADE_CTRL1 { -struct { - unsigned int auto_clk_gate_en :1; - unsigned int rot_buf_shr_out :1; - unsigned int Reserved_44 :30; + struct + { + unsigned int auto_clk_gate_en :1; + unsigned int rot_buf_shr_out :1; + unsigned int Reserved_44 :30; } bits; unsigned int u32; }; +// Define the union U_ADE_DMA_AXI_MUX +union U_ADE_DMA_AXI_MUX { + // Define the struct bits + struct + { + unsigned int rd_dma_ch1_axi_cfg : 1 ; // [0] + unsigned int rd_dma_ch2_axi_cfg : 1 ; // [1] + unsigned int rd_dma_ch3_axi_cfg : 1 ; // [2] + unsigned int rd_dma_ch4_axi_cfg : 1 ; // [3] + unsigned int rd_dma_ch5_axi_cfg : 1 ; // [4] + unsigned int rd_dma_ch6_axi_cfg : 1 ; // [5] + unsigned int rd_dma_disp_axi_cfg : 1 ; // [6] + unsigned int rd_dma_cmdq1_axi_cfg : 1 ; // [7] + unsigned int rd_dma_cmdq2_axi_cfg : 1 ; // [8] + unsigned int Reserved_14 : 1 ; // [9] + unsigned int wr_dma_ch1_axi_cfg : 1 ; // [10] + unsigned int wr_dma_ch2_axi_cfg : 1 ; // [11] + unsigned int wr_dma_ch3_axi_cfg : 1 ; // [12] + unsigned int Reserved_13 : 1 ; // [13] + unsigned int wr_dma_cmdq_axi_cfg : 1 ; // [14] + unsigned int Reserved_12 : 17 ; // [31..15] + } bits; + + // Define an unsigned member + unsigned int u32; + +}; +// Define the union U_ADE_RELOAD_DIS0 +union U_ADE_RELOAD_DIS0 { + // Define the struct bits + struct + { + unsigned int ch1_rdma_reload_dis : 1 ; // [0] + unsigned int ch2_rdma_reload_dis : 1 ; // [1] + unsigned int ch3_rdma_reload_dis : 1 ; // [2] + unsigned int ch4_rdma_reload_dis : 1 ; // [3] + unsigned int ch5_rdma_reload_dis : 1 ; // [4] + unsigned int ch6_rdma_reload_dis : 1 ; // [5] + unsigned int disp_rdma_reload_dis : 1 ; // [6] + unsigned int cmdq1_rdma_reload_dis : 1 ; // [7] + unsigned int cmdq2_rdma_reload_dis : 1 ; // [8] + unsigned int Reserved_67 : 1 ; // [9] + unsigned int ch1_wdma_reload_dis : 1 ; // [10] + unsigned int ch2_wdma_reload_dis : 1 ; // [11] + unsigned int ch3_wdma_reload_dis : 1 ; // [12] + unsigned int Reserved_66 : 1 ; // [13] + unsigned int cmdq_wdma_reload_dis : 1 ; // [14] + unsigned int clip1_reload_dis : 1 ; // [15] + unsigned int clip2_reload_dis : 1 ; // [16] + unsigned int clip3_reload_dis : 1 ; // [17] + unsigned int clip4_reload_dis : 1 ; // [18] + unsigned int clip5_reload_dis : 1 ; // [19] + unsigned int clip6_reload_dis : 1 ; // [20] + unsigned int scl1_reload_dis : 1 ; // [21] + unsigned int scl2_reload_dis : 1 ; // [22] + unsigned int scl3_reload_dis : 1 ; // [23] + unsigned int ctran1_reload_dis : 1 ; // [24] + unsigned int ctran2_reload_dis : 1 ; // [25] + unsigned int ctran3_reload_dis : 1 ; // [26] + unsigned int ctran4_reload_dis : 1 ; // [27] + unsigned int ctran5_reload_dis : 1 ; // [28] + unsigned int ctran6_reload_dis : 1 ; // [29] + unsigned int rot_reload_dis : 1 ; // [30] + unsigned int Reserved_65 : 1 ; // [31] + } bits; + + // Define an unsigned member + unsigned int u32; + +}; + union U_ADE_SOFT_RST_SEL0 { struct { unsigned int ch1_rdma_srst_sel :1; @@ -114,11 +214,11 @@ struct { static inline void set_TOP_CTL_clk_gate_en(u8 *ade_base, u32 val) { volatile union U_ADE_CTRL1 ade_ctrl1; - u8 *reg_addr = ade_base + ADE_CTRL1_REG; + u8 *addr = ade_base + ADE_CTRL1_REG; - ade_ctrl1.u32 = readl(reg_addr); + ade_ctrl1.u32 = readl(addr); ade_ctrl1.bits.auto_clk_gate_en = val; - writel(ade_ctrl1.u32, reg_addr); + writel(ade_ctrl1.u32, addr); } static inline void set_TOP_SOFT_RST_SEL0_disp_rdma(u8 *ade_base, u32 val) @@ -161,4 +261,160 @@ static inline void set_TOP_CTL_frm_end_start(u8 *ade_base, u32 val) writel(ade_ctrl.u32, reg_addr); } +inline void set_TOP_DISP_SRC_CFG(u8* ade_base, u32 val) +{ + u8* reg_addr = ade_base + ADE_DISP_SRC_CFG_REG; + writel(val, reg_addr); +} + +inline void set_TOP_SOFT_RST_SEL0(u8* ade_base, u32 val) +{ + u8* addr = ade_base + ADE_SOFT_RST_SEL0_REG; + writel(val, addr); +} + +inline void set_TOP_SOFT_RST_SEL1(u8* ade_base, u32 val) +{ + u8* addr = ade_base + ADE_SOFT_RST_SEL1_REG; + writel(val, addr); +} +inline void set_TOP_RELOAD_DIS0(u8* ade_base, u32 val) +{ + u8* addr = ade_base + ADE_RELOAD_DIS0_REG; + writel(val, addr); +} + +inline void set_TOP_RELOAD_DIS1(u8* ade_base, u32 val) +{ + u8* addr = ade_base + ADE_RELOAD_DIS1_REG; + writel(val, addr); +} + +inline void set_TOP_SOFT_RST_SEL0_cmdq1_rdma(u8* ade_base, u32 val) +{ + u8* addr = ade_base + ADE_SOFT_RST_SEL0_REG; + volatile union U_ADE_SOFT_RST_SEL0 ade_soft_rst; + + ade_soft_rst.u32 = readl(addr); + ade_soft_rst.bits.cmdq1_rdma_srst_sel = val; + writel(ade_soft_rst.u32, addr); +} + +inline void set_TOP_RELOAD_DIS0_cmdq1_rdma(u8* ade_base, u32 val) +{ + u8* addr = ade_base + ADE_RELOAD_DIS0_REG; + volatile union U_ADE_RELOAD_DIS0 ade_reload_dis; + + ade_reload_dis.u32 = readl(addr); + ade_reload_dis.bits.cmdq1_rdma_reload_dis = val; + + writel(ade_reload_dis.u32, addr); +} + +/*********** CMDQ RDMA************************/ +inline void set_CMDQ_RDMA1_PE(u8* ade_base, u32 val) +{ + u8* reg_addr = ade_base + RD_CH_CMDQ1_PE_REG; + writel(val, reg_addr); +} +inline void set_CMDQ_RDMA1_CTRL(u8* ade_base, u32 val) +{ + u8* reg_addr = ade_base + RD_CH_CMDQ1_CTRL_REG; + writel(val, reg_addr); +} +inline void set_CMDQ_RDMA1_ADDR(u8* ade_base, u32 val) +{ + u8* reg_addr = ade_base + RD_CH_CMDQ1_ADDR_REG; + writel(val, reg_addr); +} +inline void set_CMDQ_RDMA1_LEN(u8* ade_base, u32 val) +{ + u8* reg_addr = ade_base + RD_CH_CMDQ1_LEN_REG; + writel(val, reg_addr); +} +inline void set_CMDQ_RDMA1_EN(u8* ade_base, u32 val) +{ + u8* reg_addr = ade_base + RD_CH_CMDQ1_EN_REG; + writel(val, reg_addr); +} +inline void set_CMDQ_RDMA2_PE(u8* ade_base, u32 val) +{ + u8* reg_addr = ade_base + RD_CH_CMDQ2_PE_REG; + writel(val, reg_addr); +} +inline void set_CMDQ_RDMA2_CTRL(u8* ade_base, u32 val) +{ + u8* reg_addr = ade_base + RD_CH_CMDQ2_CTRL_REG; + writel(val, reg_addr); +} +inline void set_CMDQ_RDMA2_ADDR(u8* ade_base, u32 val) +{ + u8* reg_addr = ade_base + RD_CH_CMDQ2_ADDR_REG; + writel(val, reg_addr); +} +inline void set_CMDQ_RDMA2_LEN(u8* ade_base, u32 val) +{ + u8* reg_addr = ade_base + RD_CH_CMDQ2_LEN_REG; + writel(val, reg_addr); +} +inline void set_CMDQ_RDMA2_EN(u8* ade_base, u32 val) +{ + u8* reg_addr = ade_base + RD_CH_CMDQ2_EN_REG; + writel(val, reg_addr); +} + +inline void set_TOP_INTR_MASK_CPU1(u8* ade_base, u32 val) +{ + u8* reg_addr = ade_base + INTR_MASK_CPU1_REG; + writel(val, reg_addr); +} + +inline void set_TOP_DMA_AXI_MUX(u8* ade_base, u32 ch_num, u32 ch_type) +{ + //return; //Temporary modify + u8* reg_addr = ade_base + ADE_DMA_AXI_MUX_REG; + u32 axi_num; + volatile union U_ADE_DMA_AXI_MUX dma_axi_mux; + + dma_axi_mux.u32 = readl(reg_addr); + + dma_axi_mux.bits.rd_dma_cmdq2_axi_cfg = 0; + dma_axi_mux.bits.rd_dma_cmdq1_axi_cfg = 0; + if (OVERLAY_PIPE_TYPE_ONLINE == ch_type) { + axi_num = 0; + dma_axi_mux.bits.wr_dma_ch2_axi_cfg = axi_num; + } else { + axi_num = 1; + dma_axi_mux.bits.wr_dma_ch1_axi_cfg = axi_num; + dma_axi_mux.bits.wr_dma_ch3_axi_cfg = axi_num; + } + + switch (ch_num) { + case OVERLAY_PIPE_ADE_CH1: + dma_axi_mux.bits.rd_dma_ch1_axi_cfg = axi_num; + break; + case OVERLAY_PIPE_ADE_CH2: + dma_axi_mux.bits.rd_dma_ch2_axi_cfg = axi_num; + break; + case OVERLAY_PIPE_ADE_CH3: + dma_axi_mux.bits.rd_dma_ch3_axi_cfg = axi_num; + break; + case OVERLAY_PIPE_ADE_CH4: + dma_axi_mux.bits.rd_dma_ch4_axi_cfg = axi_num; + break; + case OVERLAY_PIPE_ADE_CH5: + dma_axi_mux.bits.rd_dma_ch5_axi_cfg = axi_num; + break; + case OVERLAY_PIPE_ADE_CH6: + dma_axi_mux.bits.rd_dma_ch6_axi_cfg = axi_num; + break; + case OVERLAY_PIPE_ADE_DISP: + dma_axi_mux.bits.rd_dma_disp_axi_cfg = 0;/* disp channel is always online */ + break; + default: + break; + } + + writel(dma_axi_mux.u32, reg_addr); +} #endif diff --git a/drivers/gpu/drm/hisilicon/hisi_drm_ade.c b/drivers/gpu/drm/hisilicon/hisi_drm_ade.c index cb473b05976e6e..e4beb3742c5a7b 100644 --- a/drivers/gpu/drm/hisilicon/hisi_drm_ade.c +++ b/drivers/gpu/drm/hisilicon/hisi_drm_ade.c @@ -14,6 +14,8 @@ #include #include