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/*
* Stack-less Just-In-Time compiler
*
* Copyright Zoltan Herczeg (hzmester@freemail.hu). All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are
* permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER(S) AND CONTRIBUTORS ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE COPYRIGHT HOLDER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !(defined SLJIT_CONFIG_RISCV_ATOMIC) && defined(__riscv_atomic)
/* Auto detect atomic instruction support. */
#define SLJIT_CONFIG_RISCV_ATOMIC 200
#endif /* !SLJIT_CONFIG_RISCV_ATOMIC && __riscv_atomic */
/* SLJIT_CONFIG_RISCV_ATOMIC enables/disables atomic instruction
support. Non-zero values represents the highest version of the feature
that is supported by the CPU.
Allowed values: 0 - disabled, 200 - 2.00 */
#if (defined SLJIT_CONFIG_RISCV_ATOMIC && SLJIT_CONFIG_RISCV_ATOMIC != 0)
#if SLJIT_CONFIG_RISCV_ATOMIC != 200
#error "Unsupported value for SLJIT_CONFIG_RISCV_ATOMIC"
#endif
#define RISCV_HAS_ATOMIC(x) ((SLJIT_CONFIG_RISCV_ATOMIC) >= (x))
#define RISCV_ATOMIC_INFO "a"
#else /* !SLJIT_CONFIG_RISCV_ATOMIC || SLJIT_CONFIG_RISCV_ATOMIC == 0 */
#define RISCV_HAS_ATOMIC(x) 0
#define RISCV_ATOMIC_INFO ""
#endif /* SLJIT_CONFIG_RISCV_ATOMIC && SLJIT_CONFIG_RISCV_ATOMIC != 0 */
#if !(defined SLJIT_CONFIG_RISCV_COMPRESSED) && defined(__riscv_compressed)
/* Auto detect compressed instruction support. */
#define SLJIT_CONFIG_RISCV_COMPRESSED 200
#endif /* !SLJIT_CONFIG_RISCV_COMPRESSED && __riscv_compressed */
/* SLJIT_CONFIG_RISCV_COMPRESSED enables/disables compressed instruction
support. Non-zero values represents the highest version of the feature
that is supported by the CPU.
Allowed values: 0 - disabled, 200 - 2.00 */
#if (defined SLJIT_CONFIG_RISCV_COMPRESSED && SLJIT_CONFIG_RISCV_COMPRESSED != 0)
#if SLJIT_CONFIG_RISCV_COMPRESSED != 200
#error "Unsupported value for SLJIT_CONFIG_RISCV_COMPRESSED"
#endif
#define RISCV_HAS_COMPRESSED(x) ((SLJIT_CONFIG_RISCV_COMPRESSED) >= (x))
#define RISCV_COMPRESSED_CHECK(x) (x)
#define RISCV_COMPRESSED_INFO "c"
#else /* !SLJIT_CONFIG_RISCV_COMPRESSED || SLJIT_CONFIG_RISCV_COMPRESSED == 0 */
#define RISCV_HAS_COMPRESSED(x) 0
#define RISCV_COMPRESSED_CHECK(x) 0
#define RISCV_COMPRESSED_INFO ""
#endif /* SLJIT_CONFIG_RISCV_COMPRESSED && SLJIT_CONFIG_RISCV_COMPRESSED != 0 */
#if !(defined SLJIT_CONFIG_RISCV_VECTOR) && defined(__riscv_vector)
/* Auto detect vector instruction support. */
#define SLJIT_CONFIG_RISCV_VECTOR 100
#endif /* !SLJIT_CONFIG_RISCV_VECTOR && __riscv_vector */
/* SLJIT_CONFIG_RISCV_VECTOR enables/disables vector instruction
support. Non-zero values represents the highest version of the feature
that is supported by the CPU.
Allowed values: 0 - disabled, 100 - 1.00 */
#if (defined SLJIT_CONFIG_RISCV_VECTOR && SLJIT_CONFIG_RISCV_VECTOR != 0)
#if SLJIT_CONFIG_RISCV_VECTOR != 100
#error "Unsupported value for SLJIT_CONFIG_RISCV_VECTOR"
#endif
#define RISCV_HAS_VECTOR(x) ((SLJIT_CONFIG_RISCV_VECTOR) >= (x))
#define RISCV_VECTOR_INFO "v"
#else /* !SLJIT_CONFIG_RISCV_VECTOR || SLJIT_CONFIG_RISCV_VECTOR == 0 */
#define RISCV_HAS_VECTOR(x) 0
#define RISCV_VECTOR_INFO ""
#endif /* SLJIT_CONFIG_RISCV_VECTOR && SLJIT_CONFIG_RISCV_VECTOR != 0 */
#if !(defined SLJIT_CONFIG_RISCV_BITMANIP_A) && defined(__riscv_zba)
/* Auto detect bit manipulation extension A instruction support. */
#define SLJIT_CONFIG_RISCV_BITMANIP_A 93
#endif /* !SLJIT_CONFIG_RISCV_BITMANIP_A && __riscv_zba */
/* SLJIT_CONFIG_RISCV_BITMANIP_A enables/disables bit manipulation extension A
instruction support. Non-zero values represents the highest version of the
feature that is supported by the CPU.
Allowed values: 0 - disabled, 93 - 0.93 */
#if (defined SLJIT_CONFIG_RISCV_BITMANIP_A && SLJIT_CONFIG_RISCV_BITMANIP_A != 0)
#if SLJIT_CONFIG_RISCV_BITMANIP_A != 93
#error "Unsupported value for SLJIT_CONFIG_RISCV_BITMANIP_A"
#endif
#define RISCV_HAS_BITMANIP_A(x) ((SLJIT_CONFIG_RISCV_BITMANIP_A) >= (x))
#define RISCV_BITMANIP_A_INFO "_zba"
#else /* !SLJIT_CONFIG_RISCV_BITMANIP_A || SLJIT_CONFIG_RISCV_BITMANIP_A == 0 */
#define RISCV_HAS_BITMANIP_A(x) 0
#define RISCV_BITMANIP_A_INFO ""
#endif /* SLJIT_CONFIG_RISCV_BITMANIP_A && SLJIT_CONFIG_RISCV_BITMANIP_A != 0 */
#if !(defined SLJIT_CONFIG_RISCV_BITMANIP_B) && defined(__riscv_zbb)
/* Auto detect bit manipulation extension B instruction support. */
#define SLJIT_CONFIG_RISCV_BITMANIP_B 93
#endif /* !SLJIT_CONFIG_RISCV_BITMANIP_B && __riscv_zbb */
/* SLJIT_CONFIG_RISCV_BITMANIP_B enables/disables bit manipulation extension B
instruction support. Non-zero values represents the highest version of the
feature that is supported by the CPU.
Allowed values: 0 - disabled, 93 - 0.93 */
#if (defined SLJIT_CONFIG_RISCV_BITMANIP_B && SLJIT_CONFIG_RISCV_BITMANIP_B != 0)
#if SLJIT_CONFIG_RISCV_BITMANIP_B != 93
#error "Unsupported value for SLJIT_CONFIG_RISCV_BITMANIP_B"
#endif
#define RISCV_HAS_BITMANIP_B(x) ((SLJIT_CONFIG_RISCV_BITMANIP_B) >= (x))
#define RISCV_BITMANIP_B_INFO "_zbb"
#else /* !SLJIT_CONFIG_RISCV_BITMANIP_B || SLJIT_CONFIG_RISCV_BITMANIP_B == 0 */
#define RISCV_HAS_BITMANIP_B(x) 0
#define RISCV_BITMANIP_B_INFO ""
#endif /* SLJIT_CONFIG_RISCV_BITMANIP_B && SLJIT_CONFIG_RISCV_BITMANIP_B != 0 */
#if !(defined SLJIT_CONFIG_RISCV_ICOND) && defined(__riscv_zicond)
/* Auto detect integer conditional instruction support. */
#define SLJIT_CONFIG_RISCV_ICOND 100
#endif /* !SLJIT_CONFIG_RISCV_ICOND && __riscv_zicond */
/* SLJIT_CONFIG_RISCV_ICOND enables/disables integer conditional
instruction support. Non-zero values represents the highest version of the
feature that is supported by the CPU.
Allowed values: 0 - disabled, 100 - 1.00 */
#if (defined SLJIT_CONFIG_RISCV_ICOND && SLJIT_CONFIG_RISCV_ICOND != 0)
#if SLJIT_CONFIG_RISCV_ICOND != 100
#error "Unsupported value for SLJIT_CONFIG_RISCV_ICOND"
#endif
#define RISCV_HAS_ICOND(x) ((SLJIT_CONFIG_RISCV_ICOND) >= (x))
#define RISCV_ICOND_INFO "_zicond"
#else /* !SLJIT_CONFIG_RISCV_ICOND || SLJIT_CONFIG_RISCV_ICOND == 0 */
#define RISCV_HAS_ICOND(x) 0
#define RISCV_ICOND_INFO ""
#endif /* SLJIT_CONFIG_RISCV_ICOND && SLJIT_CONFIG_RISCV_ICOND != 0 */
#if (defined SLJIT_CONFIG_RISCV_64 && SLJIT_CONFIG_RISCV_64)
#define RISCV_CHECK_COMPRESSED_JUMP(jump, diff, unit) \
(!((jump)->flags & IS_CALL) && (diff) >= (JUMP16_MIN / SSIZE_OF(unit)) && (diff) <= (JUMP16_MAX / SSIZE_OF(unit)))
#else /* !SLJIT_CONFIG_RISCV_64 */
#define RISCV_CHECK_COMPRESSED_JUMP(jump, diff, unit) \
((diff) >= (JUMP16_MIN / SSIZE_OF(unit)) && (diff) <= (JUMP16_MAX / SSIZE_OF(unit)))
#endif /* SLJIT_CONFIG_RISCV_64 */
SLJIT_API_FUNC_ATTRIBUTE const char* sljit_get_platform_name(void)
{
/* The arch string is not entirely correct since 'g' contains 'a'. */
#if (defined SLJIT_CONFIG_RISCV_32 && SLJIT_CONFIG_RISCV_32)
return "RISCV (rv32g" RISCV_ATOMIC_INFO RISCV_COMPRESSED_INFO RISCV_VECTOR_INFO RISCV_BITMANIP_A_INFO RISCV_BITMANIP_B_INFO RISCV_ICOND_INFO ")" SLJIT_CPUINFO;
#else /* !SLJIT_CONFIG_RISCV_32 */
return "RISCV (rv64g" RISCV_ATOMIC_INFO RISCV_COMPRESSED_INFO RISCV_VECTOR_INFO RISCV_BITMANIP_A_INFO RISCV_BITMANIP_B_INFO RISCV_ICOND_INFO ")" SLJIT_CPUINFO;
#endif /* SLJIT_CONFIG_RISCV_32 */
}
/* Most instructions are 32 bit long on RISCV.
Code is processed as 16 bit units. */
typedef sljit_u32 sljit_ins;
#define TMP_REG1 (SLJIT_NUMBER_OF_REGISTERS + 2)
#define TMP_REG2 (SLJIT_NUMBER_OF_REGISTERS + 3)
#define TMP_REG3 (SLJIT_NUMBER_OF_REGISTERS + 4)
#define TMP_ZERO 0
/* Flags are kept in volatile registers. */
#define EQUAL_FLAG (SLJIT_NUMBER_OF_REGISTERS + 5)
#define RETURN_ADDR_REG TMP_REG2
#define OTHER_FLAG (SLJIT_NUMBER_OF_REGISTERS + 6)
#define TMP_FREG1 (SLJIT_NUMBER_OF_FLOAT_REGISTERS + 1)
#define TMP_FREG2 (SLJIT_NUMBER_OF_FLOAT_REGISTERS + 2)
#define TMP_VREG1 (SLJIT_NUMBER_OF_VECTOR_REGISTERS + 1)
#define TMP_VREG2 (SLJIT_NUMBER_OF_VECTOR_REGISTERS + 2)
static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 7] = {
0, 10, 11, 12, 13, 14, 15, 16, 17, 29, 30, 31, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 9, 8, 2, 6, 1, 7, 5, 28
};
static const sljit_u8 freg_map[SLJIT_NUMBER_OF_FLOAT_REGISTERS + 3] = {
0, 10, 11, 12, 13, 14, 15, 16, 17, 2, 3, 4, 5, 6, 7, 28, 29, 30, 31, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 9, 8, 0, 1,
};
static const sljit_u8 vreg_map[SLJIT_NUMBER_OF_VECTOR_REGISTERS + 3] = {
0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
};
/* --------------------------------------------------------------------- */
/* Instruction forms */
/* --------------------------------------------------------------------- */
#define RD(rd) ((sljit_ins)reg_map[rd] << 7)
#define RS1(rs1) ((sljit_ins)reg_map[rs1] << 15)
#define RS2(rs2) ((sljit_ins)reg_map[rs2] << 20)
#define FRD(rd) ((sljit_ins)freg_map[rd] << 7)
#define FRS1(rs1) ((sljit_ins)freg_map[rs1] << 15)
#define FRS2(rs2) ((sljit_ins)freg_map[rs2] << 20)
#define VRD(rd) ((sljit_ins)vreg_map[rd] << 7)
#define VRS1(rs1) ((sljit_ins)vreg_map[rs1] << 15)
#define VRS2(rs2) ((sljit_ins)vreg_map[rs2] << 20)
#define IMM_I(imm) ((sljit_ins)(imm) << 20)
#define IMM_S(imm) ((((sljit_ins)(imm) & 0xfe0) << 20) | (((sljit_ins)(imm) & 0x1f) << 7))
#define C_RD(rd) ((sljit_u16)((sljit_u16)reg_map[rd] << 7))
#define C_RS2(rd) ((sljit_u16)((sljit_u16)reg_map[rd] << 2))
#define C_FRD(rd) ((sljit_u16)((sljit_u16)freg_map[rd] << 7))
#define C_FRS2(rd) ((sljit_u16)((sljit_u16)freg_map[rd] << 2))
#define C_RS1_R3(rs1) ((sljit_u16)((sljit_u16)(reg_map[rs1] & 0x7) << 7))
#define C_RS2_R3(rs2) ((sljit_u16)((sljit_u16)(reg_map[rs2] & 0x7) << 2))
#define C_FRS2_R3(rs2) ((sljit_u16)((sljit_u16)(freg_map[rs2] & 0x7) << 2))
#define C_IS_R3(r) ((reg_map[r] & 0x18) == 0x08)
#define C_IS_FR3(r) ((freg_map[r] & 0x18) == 0x08)
#define C_IMM_I(imm) ((sljit_u16)((((imm) & 0x1f) << 2) | (((imm) & 0x20) << 7)))
#define C_LD32_SP(imm) ((sljit_u16)((((imm) & 0x1c) << 2) | (((imm) & 0x20) << 7) | (((imm) & 0xc0) >> 4)))
#define C_ST32_SP(imm) ((sljit_u16)((((imm) & 0x3c) << 7) | (((imm) & 0xc0) << 1)))
#define C_LD64_SP(imm) ((sljit_u16)((((imm) & 0x18) << 2) | (((imm) & 0x20) << 7) | (((imm) & 0x1c0) >> 4)))
#define C_ST64_SP(imm) ((sljit_u16)((((imm) & 0x38) << 7) | (((imm) & 0x1c0) << 1)))
#define C_MEM32(imm) ((sljit_u16)((((imm) & 0x4) << 4) | (((imm) & 0x38) << 7) | (((imm) & 0x40) >> 1)))
#define C_MEM64(imm) ((sljit_u16)((((imm) & 0x38) << 7) | (((imm) & 0xc0) >> 1)))
#define C_BRN16(imm) ((sljit_u16)((((imm) & 0x6) << 2) | (((imm) & 0x18) << 7) | (((imm) & 0x20) >> 3) | (((imm) & 0xc0) >> 1) | (((imm) & 0x100) << 4)))
#define C_JMP16(imm) ((sljit_u16)((((imm) & 0xb40) << 1) | (((imm) & 0xe) << 2) | (((imm) & 0x10) << 7) | (((imm) & 0x20) >> 3) | (((imm) & 0x80) >> 1) | (((imm) & 0x400) >> 2)))
/* Represents funct(i) parts of the instructions. */
#define OPC(o) ((sljit_ins)(o))
#define C_OPC(o1, o2) ((sljit_u16)((o1) | ((o2) << 13)))
#define F3(f) ((sljit_ins)(f) << 12)
#define F12(f) ((sljit_ins)(f) << 20)
#define F7(f) ((sljit_ins)(f) << 25)
/* Vector instruction types. */
#define OPFVF (F3(0x5) | OPC(0x57))
#define OPFVV (F3(0x1) | OPC(0x57))
#define OPIVI (F3(0x3) | OPC(0x57))
#define OPIVV (F3(0x0) | OPC(0x57))
#define OPIVX (F3(0x4) | OPC(0x57))
#define OPMVV (F3(0x2) | OPC(0x57))
#define OPMVX (F3(0x6) | OPC(0x57))
#define ADD (F7(0x0) | F3(0x0) | OPC(0x33))
#define ADDI (F3(0x0) | OPC(0x13))
#define AND (F7(0x0) | F3(0x7) | OPC(0x33))
#define ANDI (F3(0x7) | OPC(0x13))
#define AUIPC (OPC(0x17))
#define BEQ (F3(0x0) | OPC(0x63))
#define BNE (F3(0x1) | OPC(0x63))
#define BLT (F3(0x4) | OPC(0x63))
#define BGE (F3(0x5) | OPC(0x63))
#define BLTU (F3(0x6) | OPC(0x63))
#define BGEU (F3(0x7) | OPC(0x63))
/* C_*: compressed */
#define C_ADD (C_OPC(0x2, 0x4) | (sljit_u16)(1 << 12))
#define C_ADDI (C_OPC(0x1, 0x0))
#define C_ADDIW (C_OPC(0x1, 0x1))
#define C_ADDW (C_OPC(0x1, 0x4) | (sljit_u16)(7 << 10) | (sljit_u16)(1 << 5))
#define C_ADDI16SP (C_OPC(0x1, 0x3) | (sljit_u16)(2 << 7))
#define C_AND (C_OPC(0x1, 0x4) | (sljit_u16)(3 << 10) | (sljit_u16)(3 << 5))
#define C_ANDI (C_OPC(0x1, 0x4) | (sljit_u16)(2 << 10))
#define C_BEQZ (C_OPC(0x1, 0x6))
#define C_BNEZ (C_OPC(0x1, 0x7))
#define C_EBREAK (C_OPC(0x2, 0x4) | (sljit_u16)(1 << 12))
#define C_FLDSP (C_OPC(0x2, 0x1))
#define C_FLWSP (C_OPC(0x2, 0x3))
#define C_FSD (C_OPC(0x0, 0x5))
#define C_FSDSP (C_OPC(0x2, 0x5))
#define C_FSW (C_OPC(0x0, 0x7))
#define C_FSWSP (C_OPC(0x2, 0x7))
#define C_J (C_OPC(0x1, 0x5))
#define C_JR (C_OPC(0x2, 0x4))
#if (defined SLJIT_CONFIG_RISCV_32 && SLJIT_CONFIG_RISCV_32)
#define C_JAL (C_OPC(0x1, 0x1))
#endif
#define C_JALR (C_OPC(0x2, 0x4) | (sljit_u16)(1 << 12))
#define C_LI (C_OPC(0x1, 0x2))
#define C_LUI (C_OPC(0x1, 0x3))
#define C_LDSP (C_OPC(0x2, 0x3))
#define C_LWSP (C_OPC(0x2, 0x2))
#define C_MV (C_OPC(0x2, 0x4))
#define C_NOP (C_OPC(0x1, 0x0))
#define C_SD (C_OPC(0x0, 0x7))
#define C_SDSP (C_OPC(0x2, 0x7))
#define C_SLLI (C_OPC(0x2, 0x0))
#define C_OR (C_OPC(0x1, 0x4) | (sljit_u16)(3 << 10) | (sljit_u16)(2 << 5))
#define C_SRAI (C_OPC(0x1, 0x4) | (sljit_u16)(1 << 10))
#define C_SRLI (C_OPC(0x1, 0x4) | (sljit_u16)(0 << 10))
#define C_SUB (C_OPC(0x1, 0x4) | (sljit_u16)(3 << 10) | (sljit_u16)(0 << 5))
#define C_SW (C_OPC(0x0, 0x6))
#define C_SWSP (C_OPC(0x2, 0x6))
#define C_XOR (C_OPC(0x1, 0x4) | (sljit_u16)(3 << 10) | (sljit_u16)(1 << 5))
/* CLZ / CTZ: zbb */
#define CLZ (F7(0x30) | F3(0x1) | OPC(0x13))
#define CTZ (F7(0x30) | F12(0x1) | F3(0x1) | OPC(0x13))
#define CZERO_EQZ (F7(0x7) | F3(0x5) | OPC(0x33))
#define CZERO_NEZ (F7(0x7) | F3(0x7) | OPC(0x33))
#define DIV (F7(0x1) | F3(0x4) | OPC(0x33))
#define DIVU (F7(0x1) | F3(0x5) | OPC(0x33))
#define EBREAK (F12(0x1) | F3(0x0) | OPC(0x73))
#define FADD_S (F7(0x0) | F3(0x7) | OPC(0x53))
#define FDIV_S (F7(0xc) | F3(0x7) | OPC(0x53))
#define FENCE (F3(0x0) | OPC(0xf))
#define FEQ_S (F7(0x50) | F3(0x2) | OPC(0x53))
#define FLD (F3(0x3) | OPC(0x7))
#define FLE_S (F7(0x50) | F3(0x0) | OPC(0x53))
#define FLT_S (F7(0x50) | F3(0x1) | OPC(0x53))
/* These conversion opcodes are partly defined. */
#define FCVT_S_D (F7(0x20) | OPC(0x53))
#define FCVT_S_W (F7(0x68) | OPC(0x53))
#define FCVT_S_WU (F7(0x68) | F12(0x1) | OPC(0x53))
#define FCVT_W_S (F7(0x60) | F3(0x1) | OPC(0x53))
#define FMUL_S (F7(0x8) | F3(0x7) | OPC(0x53))
#define FMV_X_W (F7(0x70) | F3(0x0) | OPC(0x53))
#define FMV_W_X (F7(0x78) | F3(0x0) | OPC(0x53))
#define FSD (F3(0x3) | OPC(0x27))
#define FSGNJ_S (F7(0x10) | F3(0x0) | OPC(0x53))
#define FSGNJN_S (F7(0x10) | F3(0x1) | OPC(0x53))
#define FSGNJX_S (F7(0x10) | F3(0x2) | OPC(0x53))
#define FSUB_S (F7(0x4) | F3(0x7) | OPC(0x53))
#define FSW (F3(0x2) | OPC(0x27))
#define JAL (OPC(0x6f))
#define JALR (F3(0x0) | OPC(0x67))
#define LD (F3(0x3) | OPC(0x3))
#define LUI (OPC(0x37))
#define LW (F3(0x2) | OPC(0x3))
/* LR: atomic */
#define LR (F7(0x8) | OPC(0x2f))
#define MAX (F7(0x5) | F3(0x6) | OPC(0x33))
#define MAXU (F7(0x5) | F3(0x7) | OPC(0x33))
#define MIN (F7(0x5) | F3(0x4) | OPC(0x33))
#define MINU (F7(0x5) | F3(0x5) | OPC(0x33))
#define MUL (F7(0x1) | F3(0x0) | OPC(0x33))
#define MULH (F7(0x1) | F3(0x1) | OPC(0x33))
#define MULHU (F7(0x1) | F3(0x3) | OPC(0x33))
#define NOP ADDI
#define OR (F7(0x0) | F3(0x6) | OPC(0x33))
#define ORI (F3(0x6) | OPC(0x13))
#define REM (F7(0x1) | F3(0x6) | OPC(0x33))
#define REMU (F7(0x1) | F3(0x7) | OPC(0x33))
/* REV8 / ROL / ROR / RORI: zbb */
#if (defined SLJIT_CONFIG_RISCV_32 && SLJIT_CONFIG_RISCV_32)
#define REV8 (F12(0x698) | F3(0x5) | OPC(0x13))
#elif (defined SLJIT_CONFIG_RISCV_64 && SLJIT_CONFIG_RISCV_64)
#define REV8 (F12(0x6b8) | F3(0x5) | OPC(0x13))
#endif /* SLJIT_CONFIG_RISCV_32 */
#define ROL (F7(0x30) | F3(0x1) | OPC(0x33))
#define ROR (F7(0x30) | F3(0x5) | OPC(0x33))
#define RORI (F7(0x30) | F3(0x5) | OPC(0x13))
/* SC: atomic */
#define SC (F7(0xc) | OPC(0x2f))
#define SD (F3(0x3) | OPC(0x23))
/* SEXTB / SEXTH: zbb */
#define SEXTB (F7(0x30) | F12(0x4) | F3(0x1) | OPC(0x13))
#define SEXTH (F7(0x30) | F12(0x5) | F3(0x1) | OPC(0x13))
/* SH1ADD / SH2ADD / SH3ADD: zba */
#define SH1ADD (F7(0x10) | F3(0x2) | OPC(0x33))
#define SH2ADD (F7(0x10) | F3(0x4) | OPC(0x33))
#define SH3ADD (F7(0x10) | F3(0x6) | OPC(0x33))
#define SLL (F7(0x0) | F3(0x1) | OPC(0x33))
#define SLLI (F3(0x1) | OPC(0x13))
#define SLT (F7(0x0) | F3(0x2) | OPC(0x33))
#define SLTI (F3(0x2) | OPC(0x13))
#define SLTU (F7(0x0) | F3(0x3) | OPC(0x33))
#define SLTUI (F3(0x3) | OPC(0x13))
#define SRL (F7(0x0) | F3(0x5) | OPC(0x33))
#define SRLI (F3(0x5) | OPC(0x13))
#define SRA (F7(0x20) | F3(0x5) | OPC(0x33))
#define SRAI (F7(0x20) | F3(0x5) | OPC(0x13))
#define SUB (F7(0x20) | F3(0x0) | OPC(0x33))
#define SW (F3(0x2) | OPC(0x23))
/* V*: vector */
#define VAND_VV (F7(0x13) | OPIVV)
#define VFMV_FS (F7(0x21) | OPFVV)
#define VFMV_SF (F7(0x21) | OPFVF)
#define VFMV_VF (F7(0x2f) | OPFVF)
#define VFWCVT_FFV (F7(0x25) | (0xc << 15) | OPFVV)
#define VL (F7(0x1) | OPC(0x7))
#define VMSLE_VI (F7(0x3b) | OPIVI)
#define VMV_SX (F7(0x21) | OPMVX)
#define VMV_VI (F7(0x2f) | OPIVI)
#define VMV_VV (F7(0x2f) | OPIVV)
#define VMV_VX (F7(0x2f) | OPIVX)
#define VMV_XS (F7(0x21) | OPMVV)
#define VOR_VV (F7(0x15) | OPIVV)
#define VSETVLI (F7(0x0) | F3(0x7) | OPC(0x57))
#define VSETIVLI (F7(0x60) | F3(0x7) | OPC(0x57))
#define VS (F7(0x1) | OPC(0x27))
#define VSLIDEDOWN_VX (F7(0x1f) | OPIVX)
#define VSLIDEDOWN_VI (F7(0x1f) | OPIVI)
#define VSLIDEUP_VX (F7(0x1d) | OPIVX)
#define VSLIDEUP_VI (F7(0x1d) | OPIVI)
#define VRGATHER_VI (F7(0x19) | OPIVI)
#define VRGATHER_VV (F7(0x19) | OPIVV)
#define VXOR_VV (F7(0x17) | OPIVV)
#define VZEXT_VF2 (F7(0x25) | (0x6 << 15) | OPMVV)
#define VZEXT_VF4 (F7(0x25) | (0x4 << 15) | OPMVV)
#define VZEXT_VF8 (F7(0x25) | (0x2 << 15) | OPMVV)
#define XOR (F7(0x0) | F3(0x4) | OPC(0x33))
#define XORI (F3(0x4) | OPC(0x13))
/* ZEXTH: zbb */
#if (defined SLJIT_CONFIG_RISCV_32 && SLJIT_CONFIG_RISCV_32)
#define ZEXTH (F7(0x4) | F3(0x4) | OPC(0x33))
#else /* SLJIT_CONFIG_RISCV_64 */
#define ZEXTH (F7(0x4) | F3(0x4) | OPC(0x3B))
#endif /* SLJIT_CONFIG_RISCV_32 */
#define SIMM_MAX (0x7ff)
#define SIMM_MIN (-0x800)
#define SIMM16_MAX (0x1f)
#define SIMM16_MIN (-0x20)
#define BRANCH_MAX (0xfff)
#define BRANCH_MIN (-0x1000)
#define BRANCH16_MAX (0xff)
#define BRANCH16_MIN (-0x100)
#define JUMP_MAX (0xfffff)
#define JUMP_MIN (-0x100000)
#define JUMP16_MAX SIMM_MAX
#define JUMP16_MIN SIMM_MIN
#if (defined SLJIT_CONFIG_RISCV_64 && SLJIT_CONFIG_RISCV_64)
#define S32_MAX (0x7ffff7ffl)
#define S32_MIN (-0x80000000l)
#define S44_MAX (0x7fffffff7ffl)
#define S52_MAX (0x7ffffffffffffl)
#endif /* SLJIT_CONFIG_RISCV_64 */
#define C_ADDI_W(word) (C_ADDI | (sljit_u16)((word) << 10))
#define C_SUB_W(word) (C_SUB | (sljit_u16)((word) << 9))
#if (defined SLJIT_CONFIG_RISCV_32 && SLJIT_CONFIG_RISCV_32)
#define BRANCH_LENGTH ((sljit_ins)(3 * sizeof(sljit_ins)) << 7)
#define BRANCH16_LENGTH C_BRN16(5 * sizeof(sljit_u16))
#else /* !SLJIT_CONFIG_RISCV_32 */
#define BRANCH_LENGTH ((sljit_ins)(7 * sizeof(sljit_ins)) << 7)
#define BRANCH16_LENGTH C_BRN16(13 * sizeof(sljit_u16))
#endif /* SLJIT_CONFIG_RISCV_32 */
static sljit_s32 push_inst(struct sljit_compiler *compiler, sljit_ins ins)
{
sljit_u16 *ptr = (sljit_u16*)ensure_buf(compiler, sizeof(sljit_ins));
FAIL_IF(!ptr);
ptr[0] = (sljit_u16)ins;
ptr[1] = (sljit_u16)(ins >> 16);
compiler->size += 2;
return SLJIT_SUCCESS;
}
static sljit_s32 push_inst16(struct sljit_compiler *compiler, sljit_u16 ins)
{
sljit_u16 *ptr = (sljit_u16*)ensure_buf(compiler, sizeof(sljit_u16));
FAIL_IF(!ptr);
*ptr = ins;
compiler->size++;
return SLJIT_SUCCESS;
}
static sljit_s32 push_imm_s_inst(struct sljit_compiler *compiler, sljit_ins ins, sljit_sw imm)
{
return push_inst(compiler, ins | IMM_S(imm));
}
static SLJIT_INLINE sljit_u16* detect_jump_type(struct sljit_jump *jump, sljit_u16 *code_ptr, sljit_u16 *code, sljit_sw executable_offset)
{
sljit_sw diff, cond_diff;
sljit_uw target_addr;
sljit_uw jump_addr = (sljit_uw)code_ptr;
sljit_uw orig_addr = jump->addr;
sljit_ins ins;
#if (defined SLJIT_CONFIG_RISCV_64 && SLJIT_CONFIG_RISCV_64)
sljit_s32 jalr_offset = JUMP_MAX_SIZE - 1;
#endif /* SLJIT_CONFIG_RISCV_64 */
SLJIT_UNUSED_ARG(executable_offset);
jump->addr = jump_addr;
if (jump->flags & SLJIT_REWRITABLE_JUMP)
goto exit;
if (jump->flags & JUMP_ADDR)
target_addr = jump->u.target;
else {
SLJIT_ASSERT(jump->u.label != NULL);
target_addr = (sljit_uw)SLJIT_ADD_EXEC_OFFSET(code + jump->u.label->size, executable_offset);
if (jump->u.label->size > orig_addr)
jump_addr = (sljit_uw)(code + orig_addr);
}
diff = (sljit_sw)target_addr - (sljit_sw)SLJIT_ADD_EXEC_OFFSET(jump_addr, executable_offset);
if (jump->flags & IS_COND) {
cond_diff = diff + SSIZE_OF(ins);
if (RISCV_COMPRESSED_CHECK((jump->flags & IS_COND16))) {
SLJIT_ASSERT((code_ptr[-1] & 0xe003) == C_BEQZ || (code_ptr[-1] & 0xe003) == C_BNEZ);
cond_diff = diff + SSIZE_OF(u16);
if (diff >= BRANCH16_MIN && diff <= BRANCH16_MAX) {
code_ptr--;
code_ptr[0] = (sljit_u16)((code_ptr[0] & 0xe383) ^ 0x2000);
jump->flags |= PATCH_B | PATCH_16;
jump->addr = (sljit_uw)code_ptr;
return code_ptr;
}
}
if (cond_diff >= BRANCH_MIN && cond_diff <= BRANCH_MAX) {
if (RISCV_COMPRESSED_CHECK((jump->flags & IS_COND16))) {
/* Converting 16 bit branch to 32 bit branch. */
code_ptr--;
code_ptr[1] = (sljit_u16)(((code_ptr[0] & 0x300) >> 8) | 0x4);
code_ptr[0] = (sljit_u16)((BNE ^ ((code_ptr[0] & 0x2000) >> 1)) | ((code_ptr[0] & 0x80) << 8));
} else {
code_ptr -= 2;
code_ptr[0] = (sljit_u16)((code_ptr[0] & 0xf07f) ^ 0x1000);
code_ptr[1] = (sljit_u16)(code_ptr[1] & 0x1ff);
}
jump->flags |= PATCH_B;
jump->addr = (sljit_uw)code_ptr;
return code_ptr + 1;
}
}
if (RISCV_HAS_COMPRESSED(200) && RISCV_CHECK_COMPRESSED_JUMP(jump, diff, u8)) {
/* A conditional instruction has larger max offset
than a 16 bit jump instruction. */
SLJIT_ASSERT(!(jump->flags & IS_COND));
jump->flags |= PATCH_J | PATCH_16;
return code_ptr;
}
if (diff >= JUMP_MIN && diff <= JUMP_MAX) {
if (jump->flags & IS_COND) {
if (RISCV_COMPRESSED_CHECK((jump->flags & IS_COND16)))
code_ptr[-1] ^= (sljit_u16)(BRANCH16_LENGTH ^ C_BRN16(3 * sizeof(sljit_u16)));
else
code_ptr[-2] ^= (sljit_u16)(BRANCH_LENGTH ^ (2 * sizeof(sljit_ins) << 7));
}
jump->flags |= PATCH_J;
return code_ptr + 1;
}
#if (defined SLJIT_CONFIG_RISCV_64 && SLJIT_CONFIG_RISCV_64)
if (diff >= S32_MIN && diff <= S32_MAX) {
if (jump->flags & IS_COND) {
if (RISCV_COMPRESSED_CHECK((jump->flags & IS_COND16)))
code_ptr[-1] ^= (sljit_u16)(BRANCH16_LENGTH ^ C_BRN16(5 * sizeof(sljit_u16)));
else
code_ptr[-2] ^= (sljit_u16)(BRANCH_LENGTH ^ (3 * sizeof(sljit_ins) << 7));
}
jump->flags |= PATCH_REL32;
jalr_offset = 3;
} else if (target_addr <= (sljit_uw)S32_MAX) {
if (jump->flags & IS_COND) {
if (RISCV_COMPRESSED_CHECK((jump->flags & IS_COND16)))
code_ptr[-1] ^= (sljit_u16)(BRANCH16_LENGTH ^ C_BRN16(5 * sizeof(sljit_u16)));
else
code_ptr[-2] ^= (sljit_u16)(BRANCH_LENGTH ^ (3 * sizeof(sljit_ins) << 7));
}
jump->flags |= PATCH_ABS32;
jalr_offset = 3;
} else if (target_addr <= S44_MAX) {
if (jump->flags & IS_COND) {
if (RISCV_COMPRESSED_CHECK((jump->flags & IS_COND16)))
code_ptr[-1] ^= (sljit_u16)(BRANCH16_LENGTH ^ C_BRN16(9 * sizeof(sljit_u16)));
else
code_ptr[-2] ^= (sljit_u16)(BRANCH_LENGTH ^ (5 * sizeof(sljit_ins) << 7));
}
jump->flags |= PATCH_ABS44;
jalr_offset = 7;
} else if (target_addr <= S52_MAX) {
if (jump->flags & IS_COND) {
if (RISCV_COMPRESSED_CHECK((jump->flags & IS_COND16)))
code_ptr[-1] ^= (sljit_u16)(BRANCH16_LENGTH ^ C_BRN16(11 * sizeof(sljit_u16)));
else
code_ptr[-2] ^= (sljit_u16)(BRANCH_LENGTH ^ (6 * sizeof(sljit_ins) << 7));
}
jump->flags |= PATCH_ABS52;
jalr_offset = 9;
}
#endif /* SLJIT_CONFIG_RISCV_64 */
exit:
ins = JALR | RS1(TMP_REG1) | IMM_I(0);
if (jump->flags & IS_CALL)
ins |= RD(RETURN_ADDR_REG);
#if (defined SLJIT_CONFIG_RISCV_32 && SLJIT_CONFIG_RISCV_32)
code_ptr[2] = (sljit_u16)ins;
code_ptr[3] = (sljit_u16)(ins >> 16);
return code_ptr + 3;
#else /* !SLJIT_CONFIG_RISCV_32 */
code_ptr += jalr_offset;
code_ptr[-1] = (sljit_u16)ins;
code_ptr[0] = (sljit_u16)(ins >> 16);
return code_ptr;
#endif /* SLJIT_CONFIG_RISCV_32 */
}
#if (defined SLJIT_CONFIG_RISCV_64 && SLJIT_CONFIG_RISCV_64)
static SLJIT_INLINE sljit_sw mov_addr_get_length(struct sljit_jump *jump, sljit_u16 *code_ptr, sljit_u16 *code, sljit_sw executable_offset)
{
sljit_uw addr;
sljit_uw jump_addr = (sljit_uw)code_ptr;
sljit_sw diff;
SLJIT_UNUSED_ARG(executable_offset);
SLJIT_ASSERT(jump->flags < (JUMP_MAX_SIZE << JUMP_SIZE_SHIFT));
if (jump->flags & JUMP_ADDR)
addr = jump->u.target;
else {
addr = (sljit_uw)SLJIT_ADD_EXEC_OFFSET(code + jump->u.label->size, executable_offset);
if (jump->u.label->size > jump->addr)
jump_addr = (sljit_uw)(code + jump->addr);
}
diff = (sljit_sw)addr - (sljit_sw)SLJIT_ADD_EXEC_OFFSET(jump_addr, executable_offset);
if (diff >= S32_MIN && diff <= S32_MAX) {
SLJIT_ASSERT(jump->flags >= ((sljit_uw)3 << JUMP_SIZE_SHIFT));
jump->flags |= PATCH_REL32;
return 3;
}
if (addr <= S32_MAX) {
SLJIT_ASSERT(jump->flags >= ((sljit_uw)3 << JUMP_SIZE_SHIFT));
jump->flags |= PATCH_ABS32;
return 3;
}
if (addr <= S44_MAX) {
SLJIT_ASSERT(jump->flags >= ((sljit_uw)7 << JUMP_SIZE_SHIFT));
jump->flags |= PATCH_ABS44;
return 7;
}
if (addr <= S52_MAX) {
SLJIT_ASSERT(jump->flags >= ((sljit_uw)9 << JUMP_SIZE_SHIFT));
jump->flags |= PATCH_ABS52;
return 9;
}
SLJIT_ASSERT(jump->flags >= ((sljit_uw)11 << JUMP_SIZE_SHIFT));
return 11;
}
#endif /* SLJIT_CONFIG_RISCV_64 */
static SLJIT_INLINE void load_addr_to_reg(struct sljit_jump *jump, sljit_sw executable_offset)
{
sljit_uw flags = jump->flags;
sljit_uw addr = (flags & JUMP_ADDR) ? jump->u.target : jump->u.label->u.addr;
sljit_ins ins;
sljit_u16 *buf = (sljit_u16 *)jump->addr;
sljit_u32 reg = (flags & JUMP_MOV_ADDR) ? *buf : TMP_REG1;
#if (defined SLJIT_CONFIG_RISCV_64 && SLJIT_CONFIG_RISCV_64)
sljit_sw high;
#endif /* SLJIT_CONFIG_RISCV_64 */
SLJIT_UNUSED_ARG(executable_offset);
#if (defined SLJIT_CONFIG_RISCV_64 && SLJIT_CONFIG_RISCV_64)
if (flags & PATCH_REL32) {
addr -= (sljit_uw)SLJIT_ADD_EXEC_OFFSET(buf, executable_offset);
SLJIT_ASSERT((sljit_sw)addr >= S32_MIN && (sljit_sw)addr <= S32_MAX);
if ((addr & 0x800) != 0)
addr += 0x1000;
ins = AUIPC | RD(reg) | (sljit_ins)((sljit_sw)addr & ~0xfff);
buf[0] = (sljit_u16)ins;
buf[1] = (sljit_u16)(ins >> 16);
if (!(flags & JUMP_MOV_ADDR)) {
ins = JALR | RS1(reg) | IMM_I(addr);
if (jump->flags & IS_CALL)
ins |= RD(RETURN_ADDR_REG);
} else
ins = ADDI | RD(reg) | RS1(reg) | IMM_I(addr);
buf[2] = (sljit_u16)ins;
buf[3] = (sljit_u16)(ins >> 16);
return;
}
#endif /* SLJIT_CONFIG_RISCV_64 */
if ((addr & 0x800) != 0)
addr += 0x1000;
#if (defined SLJIT_CONFIG_RISCV_32 && SLJIT_CONFIG_RISCV_32)
ins = LUI | RD(reg) | (sljit_ins)((sljit_sw)addr & ~0xfff);
buf[0] = (sljit_u16)ins;
buf[1] = (sljit_u16)(ins >> 16);
#else /* !SLJIT_CONFIG_RISCV_32 */
if (flags & PATCH_ABS32) {
SLJIT_ASSERT(addr <= S32_MAX);
ins = LUI | RD(reg) | (sljit_ins)((sljit_sw)addr & ~0xfff);
buf[0] = (sljit_u16)ins;
buf[1] = (sljit_u16)(ins >> 16);
} else if (flags & PATCH_ABS44) {
high = (sljit_sw)addr >> 12;
SLJIT_ASSERT((sljit_uw)high <= 0x7fffffff);
if (high > S32_MAX) {
SLJIT_ASSERT((high & 0x800) != 0);
ins = LUI | RD(reg) | (sljit_ins)0x80000000u;
buf[0] = (sljit_u16)ins;
buf[1] = (sljit_u16)(ins >> 16);
ins = XORI | RD(reg) | RS1(reg) | IMM_I(high);
buf[2] = (sljit_u16)ins;
buf[3] = (sljit_u16)(ins >> 16);
} else {
if ((high & 0x800) != 0)
high += 0x1000;
ins = LUI | RD(reg) | (sljit_ins)(high & ~0xfff);
buf[0] = (sljit_u16)ins;
buf[1] = (sljit_u16)(ins >> 16);
ins = ADDI | RD(reg) | RS1(reg) | IMM_I(high);
buf[2] = (sljit_u16)ins;
buf[3] = (sljit_u16)(ins >> 16);
}
ins = SLLI | RD(reg) | RS1(reg) | IMM_I(12);
buf[4] = (sljit_u16)ins;
buf[5] = (sljit_u16)(ins >> 16);
buf += 4;
} else {
high = (sljit_sw)addr >> 32;
if ((addr & 0x80000000l) != 0)
high = ~high;
if (flags & PATCH_ABS52) {
SLJIT_ASSERT(addr <= S52_MAX);
ins = LUI | RD(TMP_REG3) | (sljit_ins)(high << 12);
buf[0] = (sljit_u16)ins;
buf[1] = (sljit_u16)(ins >> 16);
} else {
if ((high & 0x800) != 0)
high += 0x1000;
ins = LUI | RD(TMP_REG3) | (sljit_ins)(high & ~0xfff);
buf[0] = (sljit_u16)ins;
buf[1] = (sljit_u16)(ins >> 16);
ins = ADDI | RD(TMP_REG3) | RS1(TMP_REG3) | IMM_I(high);
buf[2] = (sljit_u16)ins;
buf[3] = (sljit_u16)(ins >> 16);
buf += 2;
}
ins = LUI | RD(reg) | (sljit_ins)((sljit_sw)addr & ~0xfff);
buf[2] = (sljit_u16)ins;
buf[3] = (sljit_u16)(ins >> 16);
ins = SLLI | RD(TMP_REG3) | RS1(TMP_REG3) | IMM_I((flags & PATCH_ABS52) ? 20 : 32);
buf[4] = (sljit_u16)ins;
buf[5] = (sljit_u16)(ins >> 16);
ins = XOR | RD(reg) | RS1(reg) | RS2(TMP_REG3);
buf[6] = (sljit_u16)ins;
buf[7] = (sljit_u16)(ins >> 16);
buf += 6;
}
#endif /* !SLJIT_CONFIG_RISCV_32 */
if (!(flags & JUMP_MOV_ADDR)) {
ins = JALR | RS1(reg) | IMM_I(addr);
if (jump->flags & IS_CALL)
ins |= RD(RETURN_ADDR_REG);
} else
ins = ADDI | RD(reg) | RS1(reg) | IMM_I(addr);
buf[2] = (sljit_u16)ins;
buf[3] = (sljit_u16)(ins >> 16);
}
static SLJIT_INLINE sljit_u16 *process_extended_label(sljit_u16 *code_ptr, struct sljit_extended_label *ext_label)
{
SLJIT_ASSERT(ext_label->label.u.index == SLJIT_LABEL_ALIGNED);
return (sljit_u16*)((sljit_uw)code_ptr & ~(ext_label->data));
}
static void reduce_code_size(struct sljit_compiler *compiler)
{
struct sljit_label *label;
struct sljit_jump *jump;
struct sljit_const *const_;
SLJIT_NEXT_DEFINE_TYPES;
sljit_uw total_size;
sljit_uw size_reduce = 0;
sljit_sw diff, cond_size, cond_diff;
label = compiler->labels;
jump = compiler->jumps;
const_ = compiler->consts;
SLJIT_NEXT_INIT_TYPES();
while (1) {
SLJIT_GET_NEXT_MIN();
if (next_min_addr == SLJIT_MAX_ADDRESS)
break;
if (next_min_addr == next_label_size) {
label->size -= size_reduce;
label = label->next;
next_label_size = SLJIT_GET_NEXT_SIZE(label);
}
if (next_min_addr == next_const_addr) {
const_->addr -= size_reduce;
const_ = const_->next;
next_const_addr = SLJIT_GET_NEXT_ADDRESS(const_);
continue;
}
if (next_min_addr != next_jump_addr)
continue;
jump->addr -= size_reduce;
if (!(jump->flags & JUMP_MOV_ADDR)) {
total_size = JUMP_MAX_SIZE;
if (!(jump->flags & SLJIT_REWRITABLE_JUMP)) {
if (jump->flags & JUMP_ADDR) {
#if (defined SLJIT_CONFIG_RISCV_64 && SLJIT_CONFIG_RISCV_64)
if (jump->u.target <= S32_MAX)
total_size = 4;
else if (jump->u.target <= S44_MAX)
total_size = 8;
else if (jump->u.target <= S52_MAX)
total_size = 10;
#endif /* SLJIT_CONFIG_RISCV_64 */
} else {
/* Unit size: instruction. */
diff = (sljit_sw)jump->u.label->size - (sljit_sw)jump->addr;
if (jump->u.label->size > jump->addr) {
SLJIT_ASSERT(jump->u.label->size - size_reduce >= jump->addr);
diff -= (sljit_sw)size_reduce;
}
cond_size = RISCV_COMPRESSED_CHECK((jump->flags & IS_COND16) != 0);
cond_diff = diff + 2 - cond_size;
if (RISCV_COMPRESSED_CHECK(cond_size) && diff >= (BRANCH16_MIN / SSIZE_OF(u16)) && diff <= (BRANCH16_MAX / SSIZE_OF(u16)))
total_size = 0;
else if ((jump->flags & IS_COND) && cond_diff <= (BRANCH_MAX / SSIZE_OF(u16)) && cond_diff >= (BRANCH_MIN / SSIZE_OF(u16)))
total_size = (sljit_uw)cond_size;
else if (RISCV_HAS_COMPRESSED(200) && RISCV_CHECK_COMPRESSED_JUMP(jump, diff, u16))
total_size = 1;
else if (diff >= (JUMP_MIN / SSIZE_OF(u16)) && diff <= (JUMP_MAX / SSIZE_OF(u16)))
total_size = 2;
#if (defined SLJIT_CONFIG_RISCV_64 && SLJIT_CONFIG_RISCV_64)
else if (diff >= (S32_MIN / SSIZE_OF(u16)) && diff <= (S32_MAX / SSIZE_OF(u16)))
total_size = 4;
#endif /* SLJIT_CONFIG_RISCV_64 */
}
}
size_reduce += JUMP_MAX_SIZE - total_size;
jump->flags |= total_size << JUMP_SIZE_SHIFT;
#if (defined SLJIT_CONFIG_RISCV_64 && SLJIT_CONFIG_RISCV_64)
} else {
total_size = 11;
if (!(jump->flags & JUMP_ADDR)) {
/* Real size minus 1. Unit size: 16 bit. */
diff = (sljit_sw)jump->u.label->size - (sljit_sw)jump->addr;
if (jump->u.label->size > jump->addr) {
SLJIT_ASSERT(jump->u.label->size - size_reduce >= jump->addr);
diff -= (sljit_sw)size_reduce;
}
if (diff >= (S32_MIN / SSIZE_OF(u16)) && diff <= (S32_MAX / SSIZE_OF(u16)))
total_size = 3;
} else if (jump->u.target < S32_MAX)
total_size = 3;
else if (jump->u.target < S44_MAX)
total_size = 7;
else if (jump->u.target <= S52_MAX)
total_size = 9;
size_reduce += 11 - total_size;
jump->flags |= total_size << JUMP_SIZE_SHIFT;
#endif /* !SLJIT_CONFIG_RISCV_64 */
}
jump = jump->next;
next_jump_addr = SLJIT_GET_NEXT_ADDRESS(jump);
}
compiler->size -= size_reduce;
}
SLJIT_API_FUNC_ATTRIBUTE void* sljit_generate_code(struct sljit_compiler *compiler, sljit_s32 options, void *exec_allocator_data)
{
struct sljit_memory_fragment *buf;
sljit_u16 *code;
sljit_u16 *code_ptr;
sljit_u16 *buf_ptr;
sljit_u16 *buf_end;
sljit_uw half_count;
SLJIT_NEXT_DEFINE_TYPES;
sljit_sw executable_offset;
sljit_uw addr;
sljit_ins ins;
struct sljit_label *label;
struct sljit_jump *jump;
struct sljit_const *const_;
CHECK_ERROR_PTR();
CHECK_PTR(check_sljit_generate_code(compiler, options));
reduce_code_size(compiler);
code = (sljit_u16 *)allocate_executable_memory(compiler->size * sizeof(sljit_u16), options, exec_allocator_data, &executable_offset);
PTR_FAIL_WITH_EXEC_IF(code);
reverse_buf(compiler);
buf = compiler->buf;
code_ptr = code;
half_count = 0;
label = compiler->labels;
jump = compiler->jumps;
const_ = compiler->consts;
SLJIT_NEXT_INIT_TYPES();
SLJIT_GET_NEXT_MIN();
do {
buf_ptr = (sljit_u16*)buf->memory;
buf_end = buf_ptr + (buf->used_size >> 1);
do {
*code_ptr = *buf_ptr++;
if (next_min_addr == half_count) {
SLJIT_ASSERT(!label || label->size >= half_count);
SLJIT_ASSERT(!jump || jump->addr >= half_count);
SLJIT_ASSERT(!const_ || const_->addr >= half_count);
/* These structures are ordered by their address. */
if (next_min_addr == next_label_size) {
if (label->u.index >= SLJIT_LABEL_ALIGNED) {
code_ptr = process_extended_label(code_ptr, (struct sljit_extended_label*)label);
*code_ptr = buf_ptr[-1];
}
label->u.addr = (sljit_uw)SLJIT_ADD_EXEC_OFFSET(code_ptr, executable_offset);
label->size = (sljit_uw)(code_ptr - code);
label = label->next;
next_label_size = SLJIT_GET_NEXT_SIZE(label);
}
if (next_min_addr == next_jump_addr) {
if (!(jump->flags & JUMP_MOV_ADDR)) {
half_count = half_count - 1 + (jump->flags >> JUMP_SIZE_SHIFT);
code_ptr = detect_jump_type(jump, code_ptr, code, executable_offset);
SLJIT_ASSERT((jump->flags & PATCH_B) || ((sljit_uw)code_ptr - jump->addr < (jump->flags >> JUMP_SIZE_SHIFT) * sizeof(sljit_ins)));
} else {
#if (defined SLJIT_CONFIG_RISCV_32 && SLJIT_CONFIG_RISCV_32)
half_count += 3;
jump->addr = (sljit_uw)code_ptr;
code_ptr += 3;
#else /* !SLJIT_CONFIG_RISCV_32 */
half_count += jump->flags >> JUMP_SIZE_SHIFT;
addr = (sljit_uw)code_ptr;
code_ptr += mov_addr_get_length(jump, code_ptr, code, executable_offset);
jump->addr = addr;
#endif /* SLJIT_CONFIG_RISCV_32 */
}
jump = jump->next;
next_jump_addr = SLJIT_GET_NEXT_ADDRESS(jump);
} else if (next_min_addr == next_const_addr) {
const_->addr = (sljit_uw)code_ptr;
const_ = const_->next;
next_const_addr = SLJIT_GET_NEXT_ADDRESS(const_);
}
SLJIT_GET_NEXT_MIN();
}
code_ptr++;
half_count++;
} while (buf_ptr < buf_end);
buf = buf->next;