Skip to content
This repository was archived by the owner on Oct 5, 2018. It is now read-only.

Enable PSCI for v3.18 #15

Closed
wants to merge 2 commits into from
Closed

Enable PSCI for v3.18 #15

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
74a2352
arm64: dts: set correct memory region info
Mar 12, 2015
e3ab387
arm64: dts: enable psci in hikey
Mar 12, 2015
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
7 changes: 2 additions & 5 deletions arch/arm64/boot/dts/hi6220-hikey.dts
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -7,9 +7,6 @@

/dts-v1/;

/memreserve/ 0x00000000 0x07400000;
/memreserve/ 0x0740f000 0x1000;

#include "hikey-pinctrl.dtsi"
#include "hikey-gpio.dtsi"
#include "hi6220.dtsi"
Expand All @@ -36,9 +33,9 @@
linux,initrd-end = <0x0 0x0b600000>;
};

memory {
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x0 0x40000000>;
reg = <0x0 0x0 0x0 0x38c00000>;
};

smb {
Expand Down
52 changes: 25 additions & 27 deletions arch/arm64/boot/dts/hi6220.dtsi
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,11 @@
#include <dt-bindings/thermal/thermal.h>

/ {
psci {
compatible = "arm,psci-0.2";
method = "smc";
};

cpus {
#address-cells = <2>;
#size-cells = <0>;
Expand All @@ -16,8 +21,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x740fff8>;
enable-method = "psci";
clock-latency = <0>;
operating-points = <
/* kHz */
Expand All @@ -29,69 +33,64 @@
>;
#cooling-cells = <2>; /* min followed by max */
};

cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x740fff8>;
clock-latency = <0>;
enable-method = "psci";
};

cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x740fff8>;
clock-latency = <0>;
enable-method = "psci";
};

cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x740fff8>;
clock-latency = <0>;
enable-method = "psci";
};

cpu4: cpu@4 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x100>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x740fff8>;
enable-method = "psci";
clock-latency = <0>;
operating-points = <
/* kHz */
208000 0
432000 0
729000 0
960000 0
1200000 0
960000 0
729000 0
432000 0
208000 0
>;
#cooling-cells = <2>; /* min followed by max */
};

cpu5: cpu@5 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x101>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x740fff8>;
clock-latency = <0>;
enable-method = "psci";
};

cpu6: cpu@6 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x102>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x740fff8>;
clock-latency = <0>;
enable-method = "psci";
};

cpu7: cpu@7 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x103>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x740fff8>;
clock-latency = <0>;
enable-method = "psci";
};

cpu-map {
Expand Down Expand Up @@ -216,7 +215,6 @@
<1 14 0xff08>,
<1 11 0xff08>,
<1 10 0xff08>;
clock-frequency = <1200000>;
};

smb {
Expand Down