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Anubhav-30/README.md

Hi👋, I'm Anubhav

🚀 ECE(VLSI) Student | NMIT Bangalore | RTL Design Focus

🧠 About Me

  • 🔭 Working on RTL Design using Verilog (FIFO, UART, CPU Basics)
  • 👯 Open to collaborate on VLSI / FPGA / Open Source Hardware
  • 🤝 Learning SystemVerilog, UVM & ASIC Design Flow
  • 🌱 Exploring Computer Architecture & Digital Systems
  • 💬 Ask me about Verilog, Flip-Flops, FIFO, UART
  • ⚡ Fun fact: I design logic that becomes silicon 🚀

🌐 Connect With Me

⚡ Tech Stack

💻 HDL & Programming

🛠️ VLSI Tools & Simulation

⚙️ Dev Environment

🚀 Featured Work

🔹 FIFO Design (Verilog)

  • Synchronous FIFO design
  • Testbench + GTKWave verification

🔹 UART Communication

  • UART Tx/Rx implementation
  • Frame design + simulation

🔹 Flip-Flops Collection

  • SR, JK, D Flip-Flops
  • RTL + Testbench

🔹 Basic CPU Design (WIP 🚧)

  • Fetch → Decode → Execute

📊 GitHub Stats

🐍 Contribution Snake

🔥 Contribution Graph

🏆 GitHub Trophies

🎯 Current Focus

  • RTL Design
  • FPGA
  • ASIC Preparation

⚡ Quote

“Designing digital logic today, building silicon tomorrow.” 🚀

⭐ Star my repos if you like my work!

Popular repositories Loading

  1. FIFO-Verilog FIFO-Verilog Public

    Synchronous FIFO design in Verilog with testbench and waveform verification

    Verilog

  2. traffic-light-fsm-verilog traffic-light-fsm-verilog Public

    Traffic Light Controller using FSM in Verilog (with waveform analysis)

    Verilog

  3. Anubhav-30 Anubhav-30 Public

  4. UART-verilog UART-verilog Public

    Verilog

  5. 16-BIT-CPU 16-BIT-CPU Public

    Verilog

  6. opentitan opentitan Public

    Forked from lowRISC/opentitan

    OpenTitan: Open source silicon root of trust

    SystemVerilog