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refactor: organize models, backends, contracts and train and rollout engines - #497
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Signed-off-by: vensen <vensenmu@gmail.com>
Signed-off-by: vensen <vensenmu@gmail.com>
Signed-off-by: vensen <vensenmu@gmail.com>
Set OpenMP and MKL to one thread before PyTorch imports in the CPU unit-test job. The reordered cross-configuration suite can initialize a parent thread pool before forked smoke scorers run. Preserve the scoring timeout, numerical assertions, production routing, and GPU benchmark configuration. Signed-off-by: vensen <vensenmu@gmail.com>
Map PR types to code ownership, tests, configuration, benchmarks, and documentation. Explain model and hardware implementation status, train/rollout engine boundaries, numerical evidence, and DCO sign-offs. Add a dedicated Contributor Guide under Developer Guide while preserving all top-level navigation categories. Signed-off-by: vensen <vensenmu@gmail.com>
Render directory paths and inline terms as plain text. Escape angle-bracket placeholders so they remain visible, and preserve the command examples. Signed-off-by: vensen <vensenmu@gmail.com>
Signed-off-by: vensen <vensenmu@gmail.com> Signed-off-by: OpenAI Codex <codex@openai.com>
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October 9, 2026 11:04
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October 9, 2026 11:04
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…dels Since PR RL-Align#497, scripts/ holds only compatibility shims (contributor guide, "Move files or change packaging"), and layout.json maps scripts/ws1_reference.py to tools/validation/models/. Move museglimmer_reference.py next to it. Also run the fingerprint tests in CI-Pipeline, and import manifest_identity_hash and weight_snapshot_hash from rl_engine.config.workload instead of keeping a second copy. Signed-off-by: Ryan Huang <ryankert01@gmail.com>
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…d and the TP tests to tests/distributed, following the RL-Align#497 layout Signed-off-by: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com>
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… SP tests to tests/distributed/sp An index created under torch.inference_mode() has no version counter, so reading index._version in H3SPNormAdaLNCudaOp.plan raised for both the modulated norm and the gated residual. Such an index is now planned every time (an in-place edit cannot be seen without a version), with a regression test that runs both ops under inference mode and edits the index in place. The SP tests move from tests/models/minimax_h3 to tests/distributed/sp, following the WS2 harness relocation in RL-Align#493 and the RL-Align#497 layout; imports, the layout map and the documented command are updated. Signed-off-by: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com>
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…RL-Align#497 layout Move the benchmark and plot scripts to benchmarks/distributed/, their unit tests to tests/benchmarks/ and the all-gather size test to tests/distributed/collectives/, and update the imports and usage commands. Signed-off-by: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com>
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…tors/logprob Move the backward evidence, provider evidence and plot scripts to the RL-Align#497 operator benchmark directory, repoint REPO_ROOT, and update the imports, usage commands and operator doc. Signed-off-by: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com>
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Nov 6, 2026
Add the Qwen-Image latent pack/unpack permutation (RFC RL-Align#386) with CUDA, Triton and PyTorch backends for FP32/FP16/BF16. Forward and backward are bit-exact permutations; autograd runs the inverse kernel for backward. Migrated to the RL-Align#497 layout: CUDA source under csrc/cuda/model_specific/qwenimage, backends under rl_engine/backends/{cuda,shared/triton}/model_specific/qwenimage, the reference and shape contract under rl_engine/reference/model_specific/qwenimage, shared autograd in rl_engine/ops/packing, registry entries in rl_engine/runtime/registry.py, bindings in csrc/bindings/ops.cpp, build wiring in build_tools/extensions.py, and tests under tests/models/qwenimage. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: nodeeeeee <zhangkai.nodeee@gmail.com>
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Nov 6, 2026
…with RL-Align#497 Multiplying by scale 1.0 on the plain path replaced NaNs in forward with the canonical NaN. Gate the multiply behind a compile-time apply_scale flag, and test plain forward and backward against oracles that do not use the kernels. Move the tests and benchmark to their RL-Align#497 owners, register the op through canonical modules, and drop the new rl_engine.kernels shims and provenance aliases. Revert the unrelated final_logit_softcap benchmark refactor. Signed-off-by: haotianxue31 <haotianxue31@gmail.com>
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Nov 12, 2026
…p-down-gemm Bring the PR RL-Align#497 layout refactor ("organize models, backends, contracts and train and rollout engines") onto the WS1 MLP down projection row. The row's three commits keep their content; only its placement follows the refactor's ownership rules. Conflicts (5 files) and how each was resolved: * rl_engine/kernels/registry.py, rl_engine/kernels/gtest/operator_inputs.py and rl_engine/kernels/gtest/operator_specs.py: take the refactor's content. Those paths are compatibility shims now, so the row is not added there; its registrations move to rl_engine/runtime/registry.py (the OpBackend entries plus the cuda, rocm, musa and cpu priority maps) and to rl_engine/validation/operators/{operator_specs,operator_inputs}.py. * setup.py: take the refactor's thin entry point; the row's two native sources go into build_tools/extensions.py, which owns the source lists now -- csrc/cuda/gemm/mlp_down_gemm.cu in cuda_sources and csrc/cuda/gemm/mlp_down_gemm_sm90.cu in sm90_srcs. * docs/benchmarking/README.md: keep the refactor's paths and list the row's benchmark at its new path. Placement of the row, per docs/contributing/contributor-guide.md: * rl_engine/kernels/ops/cuda/linear/mlp_down_gemm.py -> rl_engine/backends/cuda/gemm/mlp_down_gemm.py * rl_engine/kernels/ops/pytorch/linear/mlp_down_gemm.py -> rl_engine/reference/gemm/mlp_down_gemm.py * rl_engine/kernels/ops/triton/linear/mlp_down_gemm.py -> rl_engine/backends/shared/triton/gemm/mlp_down_gemm.py * tests/test_mlp_down_gemm.py, tests/test_mlp_down_gemm_triton.py -> tests/ops/gemm/ * benchmarks/benchmark_mlp_down_gemm.py -> benchmarks/operators/gemm/benchmark_mlp_down_gemm.py The moved implementations, the operator page, the benchmark, the WS1 gtest launcher and the WS1 GPU workflow now import/name the canonical modules (rl_engine.backends.cuda.gemm, rl_engine.reference.gemm, rl_engine.backends.shared.triton.gemm, rl_engine.runtime.registry, rl_engine.validation.operators.*, rl_engine.backends.extension, rl_engine.ops.autograd.backward_runtime, rl_engine.runtime.policy). No new implementation is left under a compatibility path; the row has no legacy imports of its own to preserve. The row is also listed in benchmarks/README.md and in the WS1 GPU gate (ci/scripts/run_ws1_gtest.sh, .github/workflows/ws1-gtest-gpu.yml), the way the sibling mlp_up_gemm_gelu row is listed. Verification: * CPU checkout: `python -m pytest tests/runtime -q` 78 passed, 2 skipped; `python ci/run.py layout -q` 32 passed, 1 skipped; `tools/validation/operators/check_operator.py --op mlp_down_gemm --candidate pytorch --device cpu --dtype fp32 --check-grad` pass_rate=1.0000. * H100 80GB HBM3, SM90 build (KERNEL_ALIGN_FORCE_SM90=1, nvcc exit 0): `pytest tests/ops/gemm/test_mlp_down_gemm.py tests/ops/gemm/test_mlp_down_gemm_triton.py -q` 138 passed; the row's cases in `tests/validation/operators/test_ws1_gtest_gpu.py` 3 passed; `benchmarks/operators/gemm/benchmark_mlp_down_gemm.py --help` exits 0. * Known pre-existing failure, unrelated to this row: on a CUDA build `tests/runtime/test_attention_dispatch.py::test_registered_backend_resolves_with_provenance` fails (provenance["fallback"] is True). It fails identically on the refactor tip without this row, and passes on the CPU-only run. Signed-off-by: luoyueyuguang <luoyuelight@outlook.com>
This was referenced Nov 12, 2026
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Summary
This PR reorganizes RL-Kernel so model code, backend implementations, reusable operators, framework adapters, contracts, configuration, and validation utilities have clear ownership.
Public imports, backend IDs, configuration semantics, and validated CUDA/ROCm behavior remain compatible.
Repository structure
The directory-only map below shows the main ownership boundaries. Braces group sibling directories; the complete tracked hierarchy follows in expandable sections.
Model packages declare topology and operator needs. Shared operator semantics belong in ops and contracts; each platform owns its attention, GEMM, and FFN implementations under backends. Native kernels live in csrc. Cross-platform Triton implementations use backends/shared/triton, while ROCm-only Triton FFN stays in backends/rocm/ffn.
Engine-specific hooks belong in integrations/engines/rollout or integrations/engines/train. Post-training coordination belongs in orchestrators. WS1, WS2, model consistency, and ablation checks reuse these implementations through validation, with corresponding coverage under tests.
Reserved packages define where future work belongs; their presence does not establish model or hardware support. The selector and performance packages reserve space for future selection policies. Compatibility paths remain available for existing imports; new code belongs in the owning layers above.
Full directory inventory
The following groups include all 443 tracked directories at ca74261. Files and untracked build/cache outputs are omitted.
Library packages and compatibility paths (211 directories)
Tests (62 directories)
Native sources, benchmarks, configuration, build, CI, and tools (94 directories)
Documentation, examples, reports, and retained helpers (76 directories)
See the Contributor Guide for directory placement rules and the migration map for old-to-new paths.
Main changes
Validation
No refactor-caused functional, numerical, or end-to-end performance regression was observed on CUDA or ROCm. GPU means below use rounds 2 and 3; round 1 is warmup.
CUDA H100
CUDA strict R/R had zero mismatches in the selected rounds. Main-versus-refactor strict trajectories were raw-byte identical across 2,136 tensors, 6,963,648 tensor elements, 2,968 scalar values, and four publications of 399 parameters.
ROCm MI300X
ROCm strict R/R had zero bitwise mismatches in all 129,729 checked elements across all three rounds. In rounds 2 and 3, all 93,851 checked elements and all 16 selected samples were bitwise exact. The strict mean end-to-end time improved from the previous 59.866968 s result to 59.192035 s.
Path and test coverage
Performance numbers apply to the tested configurations and are regression evidence, not universal hardware claims.