[yhl-amd]

Summary

DeepSeek-V4.1-Flash starts and serves on gfx1250 (MI455X) at TP4 and DEP4, with its FP8 linears and index scoring on AITER's FlyDSL kernels.

Depends on ROCm/aiter#6863 (FlyDSL paged FP8 MQA logits, merged) and ROCm/aiter#6864 (FlyDSL batched mxfp8_32 GEMM with 32x32 weight scales and K tails).

Run on gfx1250

• Mono decode's persistent kernels are gfx950 code (wave64, MFMA, permlane32) and fail to compile on gfx1250. Mono's shared deployment checks now refuse any arch but gfx950, so V4.1 (and DSpark's draft and verify) take the unfused path there. The arch is read on use through deployment._gfx(), so the module still imports without aiter.jit; tests pin it to gfx950 (autouse fixture) and one test patches it back.
• The fixed-order router GEMV is the same gfx950 bf16 MFMA tile; router_supported is gfx950-only, elsewhere the gate's own GEMM routes.

FlyDSL kernels on gfx1250

• Every FP8 linear with 32x32 weight scales (wqkv_a, wq_b, wo_b, the indexer's wq_b, DSpark's main_proj, Engram's wkv) and the grouped wo_a run on the FlyDSL mxfp8_32 GEMM, which reads the 32x32 scale as stored; a K that 128 does not divide (the shared expert's down projection, K = 576 at TP4) runs as a ragged last k-tile.
• FP8 index scoring (indexer/score.py) uses flydsl_fp8_paged_mqa_logits on gfx1250, over the same packed, preshuffled 8-row-page cache and with the same arguments as the Triton kernel. This is the shared paged scorer, so any model using it on gfx1250 takes the FlyDSL kernel; other archs are unchanged.

Engram under DP attention (DEP4)

• With DP attention every rank registers its Engram tables whole, and DEP4 needed ATOM_ENGRAM_UVA=0: a layer's scales and values share a page once widened for cudaHostRegister, and HIP refuses the overlapping registration. Registration now goes through a process-wide, reference-counted set of page-locked runs, and a refused registration clears HIP's last error.
• Tables are read through a shared read-only mapping of the shard instead of safe_open's private mapping, so registration pins the same page-cache pages for every rank instead of copying each table per rank. The TP path is unchanged.

Docs

recipes/DeepSeek-V4.1-Flash.md gains a gfx1250 (MI455X) section: TP4 / DEP4 launch commands, the differences from gfx950, and GSM8K results.

Test plan

• Non-GPU unit tests (CI's run_unit_tests.sh on CPU torch): all pass except tests/test_otel_scheduler.py::test_engine_initializes_tracing_before_ready, which also fails on main at 11a2d56.
• black --check / ruff check clean on the changed files.
• gfx1250 (MI455X, 4 GPUs): TP4 and DEP4 serve DeepSeek-V4.1-Flash; DEP4 starts without ATOM_ENGRAM_UVA=0. GSM8K 3-shot: TP4 0.9257, TP4 + DSpark5 0.9257 (MI355X 0.9242).

Note: this branch also carries 99908e1 from #2694 (NidhoggD1, unchanged) so the non-GPU unit tests pass; tests/test_otel_scheduler.py::test_engine_initializes_tracing_before_ready fails on main since #2644. It drops out on rebase once #2694 merges.

🤖 Generated with Claude Code

[github-actions]

🏷️ CI Guide

Runs automatically on every eligible PR before approval:

• ✅ Pre Checkin: Black, Ruff, catalog schema validation, non-GPU unit tests

Heavy model tests:

• ✅ Run after the PR is approved and Pre Checkin passes
• ✅ Run immediately when an approval review is submitted
• ✅ Can be requested before approval with labels

Label	Tests
ci:full	Run all heavy PR model tests: native ATOM, vLLM, and SGLang
ci:atom	Run native ATOM model accuracy tests
ci:vllm	Run ATOM vLLM OOT model accuracy tests
ci:sglang	Run ATOM SGLang model accuracy tests

Heavy jobs are skipped when the PR is not approved and no matching ci:* label is present.
Add labels via the sidebar or gh pr edit 2617 --add-label <label>