[saeid-rostami]

Motivation

Optimization of conv2d for RDNA architectures.

Technical Details

Summary

This PR improves the Triton Conv2D path on AMD RDNA GPUs for FP16/BF16 and
NCHW/NHWC workloads. It adds a repack-free NCHW 3x3 kernel, replaces the
multi-operation NCHW-to-NCHWc conversion with a single Triton kernel, improves
shape/layout/dtype-aware configuration selection, and adds tuned configurations
for gfx1100, gfx1151, and gfx1201.

The public API is unchanged.

What changed

• Add a direct NCHW 3x3 kernel that reads contiguous NCHW activations without
  materializing an NCHWc input buffer.
• Route direct NCHW only where it is profitable:
  • gfx1100 and gfx1151 use exact-shape route pins.
  • gfx1201 uses the configured spatial crossover.
  • Other shapes retain the cblocked fallback.
• Fuse NCHW padding and layout conversion into one Triton
  _nchw_to_cblocked_kernel launch, with per-architecture CONV-PREPACK JSON
  configurations.
• Avoid unnecessary hot-path work by allocating channels-last outputs directly,
  loading bias in its original dtype and promoting it inside the Triton
  epilogue, and skipping logging string construction when INFO logging is off.
• Strengthen weight-pack cache keys with device, shape, stride, dtype, tensor
  version, and block size so aliases and in-place updates cannot produce stale
  cache hits.
• Extend Conv2D config lookup with layout/dtype-specific exact-shape variants,
  followed by generic shape, M_LEQ_*, and any fallbacks.
• Keep production launches deterministic by removing runtime autotune decorators
  and candidate tables from the kernel modules. Production always consumes the
  frozen per-architecture JSON configurations.
• Add regression coverage for exact-route selection, fallback routing, complete
  shape keys, and config-variant precedence.

Performance

Tested on ResNet-50, Stable Diffusion 3.5 Medium, and
FLUX.2 Klein 9B across both FP16 and BF16.

• Each model/layout/dtype combination ran in a fresh process with a fresh
  Triton disk cache; JIT compilation is excluded from the reported kernel time.
• The benchmark flushes L2 between timed measurements.
• NCHW optimized totals use kernel+repack, so the NCHWc input-pack cost is
  included. NHWC totals are kernel-only because that path has no separate input
  pack.

gfx1201

Layout	Main total time (ms)	PR total time (ms)	Time reduction	Main aggregate TFLOPS	PR aggregate TFLOPS	TFLOPS gain
NCHW	77.45	64.18	17.1%	70.52	85.11	20.7%
NHWC	92.45	52.59	43.1%	59.08	103.86	75.8%

gfx1151

Layout	Main total time (ms)	PR total time (ms)	Time reduction	Main aggregate TFLOPS	PR aggregate TFLOPS	TFLOPS gain
NCHW	294.989	269.364	8.69%	18.52	20.28	9.51%
NHWC	343.757	247.980	27.86%	15.89	22.03	38.62%

gfx1100

Layout	Main total time (ms)	PR total time (ms)	Time reduction	Main aggregate TFLOPS	PR aggregate TFLOPS	TFLOPS gain
NCHW	83.66	79.06	5.5%	65.29	69.09	5.8%
NHWC	90.86	73.39	19.2%	60.12	74.43	23.8%

Test Plan

Test Result

Submission Checklist

• Look over the contributing guidelines at https://github.com/ROCm/ROCm/blob/develop/CONTRIBUTING.md#pull-requests.

[github-actions]

🏷️ CI Guide

Runs automatically on every PR:

• ✅ Pre-checks (submodule verification, code formatting)
• ✅ Aiter op tests (gfx942 + gfx950)
• ✅ Triton tests on MI35X (only when aiter/ops/triton/** or related paths are changed)

Extended tests (opt-in via labels):

Label	Tests
ci:gfx1250-ffm-triton	Run the five-shard gfx1250 FFM Triton test suite
ci:triton-300x	Run an additional Triton test job on MI300X in PRs; main branch always runs both MI35X and MI300X
ci:sglang	SGLang integration tests: DeepSeek-R1-MXFP4 accuracy, Qwen 3.5 accuracy
ci:atom	ATOM benchmark: DeepSeek-R1-0528, GPT-OSS-120B
ci:atom_full	ATOM accuracy suite for PR and main models from ATOM models_accuracy.json
ci:vllm	vLLM benchmark: GPT-OSS-120B, DeepSeek-R1-0528, Kimi-K2.5
ci:all	All standard extended tests (excludes ci:atom_full)

Only add ci:atom_full for FlyDSL or Triton upgrades.
Add labels via the sidebar or gh pr edit 4869 --add-label <label>

PR title tags:
Component tags ([Triton/Gluon], [HIP], [CK], [ASM], ...) are added to the PR title automatically from the changed files and re-synced on every push — change-type tags like [fix]/[Perf] and op tags like [MLA] are left untouched. Add the no-auto-title label to opt this PR out of title tagging.

[Copilot]

Pull request overview

This PR optimizes the Triton Conv2D implementation for AMD RDNA architectures by adding a repack-free direct NCHW 3×3 kernel, replacing the Python-side NCHW→NCHWc conversion with a single Triton packing kernel, and strengthening configuration/routing selection (including new per-arch JSON configs and routing regression tests) while keeping the public API unchanged.

Changes:

• Add a direct NCHW 3×3 route and kernel, and update routing to select it only when profitable (exact-shape pins or spatial crossover).
• Fuse NCHW→NCHWc activation packing into one Triton kernel and add CONV-PREPACK per-arch configs.
• Extend conv config lookup with layout/dtype variants and add routing/config regression tests + bench labeling updates.

Reviewed changes

Copilot reviewed 37 out of 37 changed files in this pull request and generated 1 comment.

Show a summary per file

File	Description
op_tests/triton_tests/conv/test_conv2d.py	Adds routing/config-lookup regression tests and updates suite documentation/counts.
op_tests/triton_tests/conv/_helpers.py	Registers new direct method and adds a guard tied to config availability.
op_tests/op_benchmarks/triton/bench_conv2d.py	Updates route labeling helper to pass padding into routing.
aiter/ops/triton/utils/conv_config_utils.py	Adds variant-aware config lookup, prepack shape-key formatting, and config presence probing.
aiter/ops/triton/conv/README.md	Updates user-facing docs to reflect new kernel family, routing, and config tiers.
aiter/ops/triton/conv/DESIGN.md	Updates design documentation for direct NCHW routing, fused prepack, and config lookup behavior.
aiter/ops/triton/conv/conv2d.py	Adds direct NCHW 3×3 routing and wrapper, refactors 3×3 selection logic, and reduces logging overhead.
aiter/ops/triton/conv/_utils.py	Allocates NHWC outputs directly as channels-last; changes bias handling to avoid eager dtype conversion.
aiter/ops/triton/conv/_prepack.py	Strengthens weight-pack cache keys and switches NCHW→NCHWc packing to a Triton kernel launch.
aiter/ops/triton/conv/_launch.py	Adds fused NCHW→NCHWc pack launcher, adds direct NCHW 3×3 launcher, and passes config variants for selection.
aiter/ops/triton/configs/conv/gfx950-CONV-PREPACK.json	Adds tuned prepack configs for gfx950.
aiter/ops/triton/configs/conv/gfx942-CONV-PREPACK.json	Adds tuned prepack configs for gfx942.
aiter/ops/triton/configs/conv/gfx1250-CONV-PREPACK.json	Adds tuned prepack configs for gfx1250.
aiter/ops/triton/configs/conv/gfx1201-CONV-PREPACK.json	Adds tuned prepack configs for gfx1201.
aiter/ops/triton/configs/conv/gfx1200-CONV-PREPACK.json	Adds tuned prepack configs for gfx1200.
aiter/ops/triton/configs/conv/gfx1151-CONV-PREPACK.json	Adds tuned prepack configs for gfx1151.
aiter/ops/triton/configs/conv/gfx1100-CONV-PREPACK.json	Adds tuned prepack configs for gfx1100.
aiter/ops/triton/configs/conv/gfx1201-CONV-GENERAL.json	Updates tuned parameters (e.g., BLOCK_K) for gfx1201 general kernel.
aiter/ops/triton/configs/conv/gfx1151-CONV-GENERAL.json	Updates tuned parameters (e.g., BLOCK_K) for gfx1151 general kernel.
aiter/ops/triton/configs/conv/gfx1201-CONV-3X3-NHWC.json	Adds dtype-specific exact-shape pins for gfx1201 NHWC 3×3 config.
aiter/ops/triton/configs/conv/gfx1201-CONV-3X3-NCHW.json	Adds new gfx1201 direct NCHW 3×3 config table.
aiter/ops/triton/configs/conv/gfx1201-CONV-3X3-CBLOCKED.json	Adds fp16 variant pins and updates tuned parameters for gfx1201 cblocked 3×3 config.
aiter/ops/triton/configs/conv/gfx1201-CONV-1X1.json	Adds NHWC exact-shape pins for gfx1201 1×1 config.
aiter/ops/triton/configs/conv/gfx1151-CONV-WINO-F4X3-OUTPUT.json	Updates tuned Winograd output-transform config for gfx1151.
aiter/ops/triton/configs/conv/gfx1151-CONV-WINO-F4X3-INPUT.json	Updates tuned Winograd input-transform config for gfx1151.
aiter/ops/triton/configs/conv/gfx1151-CONV-WINO-F4X3-GEMM.json	Updates tuned Winograd GEMM config for gfx1151.
aiter/ops/triton/configs/conv/gfx1151-CONV-3X3-NHWC.json	Updates tuned NHWC 3×3 config for gfx1151.
aiter/ops/triton/configs/conv/gfx1151-CONV-3X3-NCHW.json	Adds new gfx1151 direct NCHW 3×3 exact-route config table.
aiter/ops/triton/configs/conv/gfx1151-CONV-3X3-CBLOCKED.json	Updates tuned cblocked 3×3 config for gfx1151.
aiter/ops/triton/configs/conv/gfx1151-CONV-1X1.json	Updates tuned 1×1 config for gfx1151 and adds variant shape maps.
aiter/ops/triton/configs/conv/gfx1100-CONV-3X3-NCHW.json	Adds new gfx1100 direct NCHW 3×3 exact-route config table.
aiter/ops/triton/_triton_kernels/conv/nchw_to_cblocked.py	Adds new Triton kernel for fused NCHW→NCHWc activation packing.
aiter/ops/triton/_triton_kernels/conv/helpers.py	Removes runtime autotune gate module from production Conv2D kernels.
aiter/ops/triton/_triton_kernels/conv/conv_general.py	Removes runtime autotune paths, adds variants plumbing, and promotes bias to fp32 in-kernel.
aiter/ops/triton/_triton_kernels/conv/conv_3x3.py	Removes runtime autotune paths, adds direct NCHW 3×3 kernel, variants plumbing, and promotes bias to fp32 in-kernel.
aiter/ops/triton/_triton_kernels/conv/conv_3x3_winograd_f4x3.py	Removes runtime autotune paths and promotes bias to fp32 in output transform.
aiter/ops/triton/_triton_kernels/conv/conv_1x1.py	Removes runtime autotune paths, adds variants plumbing, and promotes bias to fp32 in-kernel.

---

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[Copilot]

Pull request overview

Copilot reviewed 37 out of 37 changed files in this pull request and generated no new comments.

Suppressed comments (2)

aiter/ops/triton/_triton_kernels/conv/nchw_to_cblocked.py:16

• The new Triton kernel _nchw_to_cblocked_kernel is declared with @triton.jit but does not set a config-aware repr (e.g. via make_kernel_repr(...)) like the other conv kernels. Without a stable repr embedding the tuned meta-parameters, trace/profiling labels can be ambiguous and compiled-kernel caching/debuggability can regress compared to existing kernels in this directory.

def _get_config(shape_key=None, M=None, variants=()):
    return get_conv_config("CONV-PREPACK", shape_key=shape_key, M=M, variants=variants)


@triton.jit
def _nchw_to_cblocked_kernel(
    X,

aiter/ops/triton/conv/conv2d.py:620

• conv2d_nchw_3x3_direct() can be called directly, but it unconditionally performs config lookup for CONV-3X3-NCHW via _launch_3x3_nchw even on architectures where that optional JSON table is not shipped. On such devices this will fail with a low-level config-file load error rather than a clear, actionable exception. Consider guarding with has_conv_config("CONV-3X3-NCHW") and raising a ValueError explaining that direct NCHW 3x3 is only available on specific archs/configs (and that the caller should use conv2d_nchw routing instead).

[Ragua1]

Measured on gfx1150 (Radeon 890M, RDNA 3.5), Windows with native ROCm, torch 2.11.0+rocm7.15.0a20260728, Triton 3.7.1, on 2026-08-21 against main at ba59a37 and this branch at e363cf6. I maintain a downstream consumer that routes diffusion VAE-decode convolutions through aiter.ops.triton.conv. My primary interest is gfx1101 (RX 7800 XT), which I cannot measure at the moment; gfx1150 is the card I have to hand, and neither ships a conv table, so they are in the same position with respect to this PR.

The performance direction of this PR is good on this part, which is why I would like it to stay reachable. On the routes it keeps — cblocked, fp16, N=1, K=C, interleaved A-B-A-B in one session, the two runs per revision shown rather than averaged:

shape	main	this PR	change
C=512, 128×128, 3×3	10.575 / 10.640 ms	10.520 / 10.482 ms	−1 %
C=512, 256×256, 3×3	41.706 / 41.043 ms	40.992 / 40.567 ms	−1.5 %
C=256, 512×512, 3×3	41.651 / 42.563 ms	39.344 / 39.325 ms	−6.6 %
C=128, 1024×1024, 3×3	43.978 / 44.401 ms	37.485 / 37.546 ms	−15.0 %

The new packing kernel accounts for it: pack cost drops from 9.37 to 5.85 ms at 1024×1024, about 38 % cheaper than the host-side permute().contiguous() on main. Separately, conv2d_1x1(layout="nhwc") is 2.3× faster here (2.85 → 1.25 ms).

The question

On an architecture that ships no tuned table, the two revisions behave differently:

main @ ba59a37,    no config, AITER_TRITON_CONV_AUTOTUNE=0  ->  FileNotFoundError
main @ ba59a37,    no config, AITER_TRITON_CONV_AUTOTUNE=1  ->  runs, rel_l2 7.67e-04
this PR @ e363cf6, no config, AITER_TRITON_CONV_AUTOTUNE=1  ->  FileNotFoundError

Two changes combine: _triton_kernels/conv/helpers.py is deleted along with the seven AUTOTUNE_*_CONFIGS, so the env-var bypass documented in conv/README.md no longer exists; and CONV-PREPACK is a newly required per-arch family on a path that previously read no JSON at all, so it is the first lookup to fail. The per-architecture requirement goes from 7 tables to 9, and every shipped table is arch-specific. The updated README states which architectures ship one — gfx1100, gfx1151, gfx1200 and gfx1201 — and that is four of the eight in RDNA_ARCHS; the other four are gfx1030, gfx1101, gfx1102 and gfx1150, so conv2d becomes unreachable on RX 6800/6900, RX 7800 XT and 7700 XT, RX 7600 and Strix Point.

I am not claiming any of those is documented as supported; op_tests/triton_tests/conv/_helpers.py lists exactly the four that have tables, so the current state is self-consistent. The question is what the intended path is for the other four now that retuning moves out of the package, since the README paragraph describing how to run without a table is removed in this diff, and its replacement states that "candidate search spaces and the tuning driver live outside the production package".

Two observations that may make this cheap to resolve. First, on this part the config contents matter much less than their presence: a 48-combination sweep over BLOCK_M/BLOCK_N/BLOCK_K/GROUP_SIZE_M/num_warps on the four shapes above — route asserted as DIRECT_NCHW_3X3, output checked against torch.nn.functional.conv2d — reaches parity with the cblocked route at best (0.93–1.16× over three repeats), and simply borrowing a shipped table gives much the same (gfx1151 0.84×, gfx1201 0.85×). Second, it would have to be a curated default rather than arbitrary values: in the same sweep num_warps=2 with BLOCK_N=128 produced 0.05×, twenty times slower than cblocked. A nearest-architecture fallback would therefore cost very little and remove a hard failure — and has_conv_config(), which this PR adds with load_config_json(..., required=False) and a docstring calling the table optional, is already the primitive for it. (The suppressed automated comment on conv2d.py proposes exactly that as a guard for conv2d_nchw_3x3_direct(); that is one entry point, whereas on an architecture with no table at all the first mandatory get_conv_config fails inside load_config_json before any KeyError path is reached.)

On gfx1101 the picture came out a little differently — there the table contents did move the number. Measured in early August 2026 on the pre-#4869 tree, not re-verified since, and to one significant figure: repeating the comparison in a later session shifted the ratio by about two points, so I would not quote a second digit. The shipped gfx1100 table from #4265 was indistinguishable from an RDNA4 table on that card — a ratio of 1.00 against a 6–8 % spread within a single arm — so same-generation donorship was not the lever. Changing one value in the RDNA4 table — BLOCK_K 64→32 in CONV-3X3-CBLOCKED — was worth about 10 % there, while the same edit applied to the gfx1100 table was worth nothing, so the useful value is donor-specific rather than portable. And a held-out neighbour table cost about 9 % against one tuned on the card. So a neighbour table is worth far more than a hard failure, and still leaves something on the table; that ordering is what matters here.

Is a curated nearest-architecture fallback something you would consider, or is the intent that an architecture without a table goes through the offline tuning path first? Either answer is useful — it tells downstream consumers on those four architectures what to plan for.

[brunomazzottiamd]

Sharing some comments.

[saeid-rostami]

Measured on gfx1150 (Radeon 890M, RDNA 3.5), Windows with native ROCm, torch 2.11.0+rocm7.15.0a20260728, Triton 3.7.1, on 2026-08-21 against main at ba59a37 and this branch at e363cf6. I maintain a downstream consumer that routes diffusion VAE-decode convolutions through aiter.ops.triton.conv. My primary interest is gfx1101 (RX 7800 XT), which I cannot measure at the moment; gfx1150 is the card I have to hand, and neither ships a conv table, so they are in the same position with respect to this PR.

The performance direction of this PR is good on this part, which is why I would like it to stay reachable. On the routes it keeps — cblocked, fp16, N=1, K=C, interleaved A-B-A-B in one session, the two runs per revision shown rather than averaged:

shape main this PR change
C=512, 128×128, 3×3 10.575 / 10.640 ms 10.520 / 10.482 ms −1 %
C=512, 256×256, 3×3 41.706 / 41.043 ms 40.992 / 40.567 ms −1.5 %
C=256, 512×512, 3×3 41.651 / 42.563 ms 39.344 / 39.325 ms −6.6 %
C=128, 1024×1024, 3×3 43.978 / 44.401 ms 37.485 / 37.546 ms −15.0 %
The new packing kernel accounts for it: pack cost drops from 9.37 to 5.85 ms at 1024×1024, about 38 % cheaper than the host-side permute().contiguous() on main. Separately, conv2d_1x1(layout="nhwc") is 2.3× faster here (2.85 → 1.25 ms).

The question

On an architecture that ships no tuned table, the two revisions behave differently:

main @ ba59a37,    no config, AITER_TRITON_CONV_AUTOTUNE=0  ->  FileNotFoundError
main @ ba59a37,    no config, AITER_TRITON_CONV_AUTOTUNE=1  ->  runs, rel_l2 7.67e-04
this PR @ e363cf6, no config, AITER_TRITON_CONV_AUTOTUNE=1  ->  FileNotFoundError

Two changes combine: _triton_kernels/conv/helpers.py is deleted along with the seven AUTOTUNE_*_CONFIGS, so the env-var bypass documented in conv/README.md no longer exists; and CONV-PREPACK is a newly required per-arch family on a path that previously read no JSON at all, so it is the first lookup to fail. The per-architecture requirement goes from 7 tables to 9, and every shipped table is arch-specific. The updated README states which architectures ship one — gfx1100, gfx1151, gfx1200 and gfx1201 — and that is four of the eight in RDNA_ARCHS; the other four are gfx1030, gfx1101, gfx1102 and gfx1150, so conv2d becomes unreachable on RX 6800/6900, RX 7800 XT and 7700 XT, RX 7600 and Strix Point.

I am not claiming any of those is documented as supported; op_tests/triton_tests/conv/_helpers.py lists exactly the four that have tables, so the current state is self-consistent. The question is what the intended path is for the other four now that retuning moves out of the package, since the README paragraph describing how to run without a table is removed in this diff, and its replacement states that "candidate search spaces and the tuning driver live outside the production package".

Two observations that may make this cheap to resolve. First, on this part the config contents matter much less than their presence: a 48-combination sweep over BLOCK_M/BLOCK_N/BLOCK_K/GROUP_SIZE_M/num_warps on the four shapes above — route asserted as DIRECT_NCHW_3X3, output checked against torch.nn.functional.conv2d — reaches parity with the cblocked route at best (0.93–1.16× over three repeats), and simply borrowing a shipped table gives much the same (gfx1151 0.84×, gfx1201 0.85×). Second, it would have to be a curated default rather than arbitrary values: in the same sweep num_warps=2 with BLOCK_N=128 produced 0.05×, twenty times slower than cblocked. A nearest-architecture fallback would therefore cost very little and remove a hard failure — and has_conv_config(), which this PR adds with load_config_json(..., required=False) and a docstring calling the table optional, is already the primitive for it. (The suppressed automated comment on conv2d.py proposes exactly that as a guard for conv2d_nchw_3x3_direct(); that is one entry point, whereas on an architecture with no table at all the first mandatory get_conv_config fails inside load_config_json before any KeyError path is reached.)

On gfx1101 the picture came out a little differently — there the table contents did move the number. Measured in early August 2026 on the pre-#4869 tree, not re-verified since, and to one significant figure: repeating the comparison in a later session shifted the ratio by about two points, so I would not quote a second digit. The shipped gfx1100 table from #4265 was indistinguishable from an RDNA4 table on that card — a ratio of 1.00 against a 6–8 % spread within a single arm — so same-generation donorship was not the lever. Changing one value in the RDNA4 table — BLOCK_K 64→32 in CONV-3X3-CBLOCKED — was worth about 10 % there, while the same edit applied to the gfx1100 table was worth nothing, so the useful value is donor-specific rather than portable. And a held-out neighbour table cost about 9 % against one tuned on the card. So a neighbour table is worth far more than a hard failure, and still leaves something on the table; that ordering is what matters here.

Is a curated nearest-architecture fallback something you would consider, or is the intent that an architecture without a table goes through the offline tuning path first? Either answer is useful — it tells downstream consumers on those four architectures what to plan for.

@Ragua1
Thanks for the detailed measurements and analysis. It is especially useful to see that the packing kernel improves the larger cblocked workloads on gfx1150.
The removal of AITER_TRITON_CONV_AUTOTUNE and the in-kernel autotuning configurations was intentional. After discussing this internally, I was asked to follow the AITER policy that production Triton kernels should not perform runtime autotuning or carry autotuning search spaces.
The intended workflow for an architecture without Conv2D configuration files is to tune the kernels offline, add the resulting per-architecture JSON configuration files, and submit them to AITER in a PR. We do not currently intend to select an arbitrary or nearest-architecture configuration automatically, since—as your gfx1101 results also demonstrate—configurations are not always portable and a poorly matched fallback can cause a substantial performance regression.
Therefore, the current failure on architectures without the required configuration tables is expected under this policy. If you would like to add support for gfx1101, gfx1102, gfx1150, or another missing architecture, please tune and submit the corresponding Conv2D configuration files and add me as a reviewer. I would be happy to help review and validate them.

[Copilot]

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[Copilot]

Pull request overview

Copilot reviewed 37 out of 37 changed files in this pull request and generated 1 comment.

Suppressed comments (1)

aiter/ops/triton/_triton_kernels/conv/nchw_to_cblocked.py:15

• New Triton kernel _nchw_to_cblocked_kernel is missing a config-aware repr=make_kernel_repr(...). Other Conv2D kernels set a repr so traces embed the tuned config; without it, profiling/debugging can’t reliably distinguish different BLOCK_C/BLOCK_M configs for this kernel.

@triton.jit
def _nchw_to_cblocked_kernel(

[Copilot]

Pull request overview

Copilot reviewed 37 out of 37 changed files in this pull request and generated no new comments.

Suppressed comments (1)

Previously missed (1) — in code that hasn't changed since the last review.

aiter/ops/triton/conv/conv2d.py:160

• In _resolve_route's NHWC branch, the router ignores the "general" result from _select_3x3_method (which returns "general" for narrow C). This makes the narrow-channel heuristic ineffective for NHWC 3x3 and can route small-C workloads to the NHWC 3x3 kernel even when the selector chose the general kernel.

[brunomazzottiamd]

LGTM!

[Copilot]

Pull request overview

Copilot reviewed 37 out of 37 changed files in this pull request and generated 1 comment.