[fsx950223]

Motivation

Cleanups in the FlyDSL PA decode wrapper and kernels. The reducer launcher took two partition limits where one is enough, and several spots duplicated helpers that aiter or FlyDSL already provide.

Changes

• One reducer partition bound: launch_pa_decode_ps_reduce takes a single max_partitions, which is the tight per-call bound. pa_decode computes it from the plan cap, plan capacity, context tiles and the sliding-window cap, and the separate partition_bound argument is removed.
  • Small bounds still compile exactly, so short contexts keep the register-only reducer.
  • Above a wave, the power-of-two round-up is now capped by the device CU count instead of the plan's max_partitions. With a non-default plan cap that isn't a power of two, the compiled bound can round past it (for example 100 → 128). This is safe because the reducer's per-sequence buffer bound zero-fills partitions beyond the live count.
• Shared helpers instead of local copies:
  • pa_decode uses dtypes.fp8 instead of its own arch → FP8 dtype table. The supported-arch check stays.
  • The reducer uses tensor_shim._FX_ELEM instead of a local _DTYPE_MAP, and still accepts only f32, f16 and bf16.
  • The gfx1250 WMMA and FP8-conversion calls use fx.as_ir_value instead of tensor_shim._to_raw.
• gfx1250 thread count: Gfx1250Traits.BLOCK_THREADS (NWARP * WAVE = 128) replaces the hardcoded 128 in known_block_size, the launch block, the direct-output copy loop and stage_vector_dma. It's a class constant, not a dataclass field, so traits cache keys don't change.
• sliding_window: pa_decode and plan_pa_decode treat any nonpositive value as disabled instead of raising for values below -1. The docstrings say so.

Test

• op_tests/test_flydsl_pa_decode.py on gfx1250 with FlyDSL 0.4.0: 119 passed, 5 skipped.
• plan_pa_decode(..., sliding_window=-5) builds the same plan as -1.
• gfx942 and gfx950 were not run on hardware. The reducer-bound, dtypes.fp8 and _FX_ELEM changes also apply there.
• black and ruff pass.

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🏷️ CI Guide

Runs automatically on every PR:

• ✅ Pre-checks (submodule verification, code formatting)
• ✅ Aiter op tests (gfx942 + gfx950)
• ✅ Triton tests on MI35X (only when aiter/ops/triton/** or related paths are changed)

Extended tests (opt-in via labels):

Label	Tests
ci:gfx1250-ffm-triton	Run the five-shard gfx1250 FFM Triton test suite
ci:triton-300x	Run an additional Triton test job on MI300X in PRs (added automatically when gfx942 configs change); main branch always runs both MI35X and MI300X
ci:triton-355	Run the full Triton test suite on MI35X, not only the tests the change affects
ci:windows	Windows JIT op smoke test on the gfx1201 ROCm runner
ci:multi-gpu	Aiter multi-GPU tests on the 8-GPU runner
ci:sglang	SGLang integration tests: DeepSeek-R1-MXFP4 accuracy, Qwen 3.5 accuracy
ci:atom	ATOM benchmark: DeepSeek-R1-0528, GPT-OSS-120B
ci:atom_full	ATOM accuracy suite for PR and main models from ATOM models_accuracy.json
ci:vllm	vLLM benchmark: DeepSeek-V4-Pro, MiniMax-M3-MXFP4
ci:all	All standard extended tests (excludes ci:atom_full)

Only add ci:atom_full for FlyDSL or Triton upgrades.
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