WIV64, thrid attempt on implementing RISC-V

WIV64 is a pipelined RISC-V CPU currently supporting RV64IAC_Zicsr_Zifencei

This is my third attempt to implement a RV64I ISA and learning in the process. Keep in mind this is a hobby-like project so it can contain bugs on things outside the core itself.

Features:

• RV64IAC_Zicsr_Zifencei
• Instruction cache and data cache(4KB each)
• M-mode
• DM non-ISA extension conforming to the "Minimal RISC-V Debug Specification 1.0-STABLE"
• JTAG-TAP (DM can access all GPRs and CSRs and Abstract Access Memory when core is halted)

Sample implementation features:

• Onboard BRAM as RAM/ROM
• DDR3 controller interface for Xilinx MIG7
• Simple UART Tx
• Simple Spi controller (supports all modes)
• Test register, for riscv tests(not on implementation)
• Debug 7Seg outputting the state of the core

Unsupported fatures:

• M extension, converting it to RV64GC
• U-mode
• S-mode
• Convert caches to BRAM
• Maybe more things

License

Copyright © 2024, Jesús Sanz del Rey

WIV64 by Jesús Sanz del Rey is licensed under Attribution-NonCommercial-ShareAlike 4.0 International

If another type of license is needed contact me directly.