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XACKIES/README.md

👋 Hi there, I'm MACKIES (XACKIES)

“ Believes in living life to the fullest, constantly seeking new opportunities to learn and grow.”

🧠 About Me

  • 👨‍🎓 I am currently a 4th-year student in Electronics and Telecommunication Engineering at KMUTT.
  • 🚀 Passionate about Hardware Electronics Engineering : ASIC, FPGA, Embedded System, PCB - Design
  • 🌐 LinkedIn site: Kittiphop Phanthachart
  • 📫 Contact: p.kittiphop.work@gmail.com

📌 Featured Projects

🔹RISC-CPU-Design-of-a-Single-Cycle-MIPS-Softcore-Processor-in-Verilog-HDL

Designed Softcore MIPS Processor : Single-Cycle RISC Architecture in Verilog HDL

🔹MAC32010 Chip : Digital Low-Pass Filter Core (Custom ASIC Design)

Custom ASIC implementation of a Verilog FIR low-pass filter core using OpenLane. Adapted RTL from an FPGA project and performed synthesis, floorplanning, placement, routing, and verification on Sky130 PDK.

🔹 MAC101-Chip-H-Bridge-Gate-Controller (Custom ASIC Design)

ASIC/IC-Design , Gate control of H Bridge Driver for Motor-Drive , Non-Inverting-Buck-Boost Converter , Inverter

🔹 RTL-Design-of-FIR-Filter-on-FPGA-using-Verilog

Designed a FIR Filter with coefficients calculated in Python and implemented fixed-point arithmetic for FPGA processing.

🔹 RTL-Design-of-IIR-Filter-as-Digital-Envelope-Detector

Designed Digital Envelope Detector in Verilog using a first-order IIR Low-Pass filter. useful in ASK/FSK demodulation, and Signal detection.

🔹 DDS-with-Uart-interface-on-FPGA

Direct Digital Synthesizer on FPGA with UART control interface.

🔹 SALVS-01: Specify Animals Location Via Sound

Nanosatellite project concept to triangulate animal position based on sound.

🔹 LC-Ladder-Bandpass-RF---Filter-Design-436MHz-at-KNACSAT-3

Designed LC Ladder RF bandpass filter at 436MHz with a bandwidth of 30MHz

📊 GitHub Stats

XACKIES's GitHub stats

🔧 Technical Skills

🖥 Programming IDEs

🔧 Programming Tools

🧪 Simulation Tools

🖊 EDA

💻 Coding Languages

Pinned Loading

  1. RISC-CPU-Design-of-a-Single-Cycle-MIPS-Softcore-Processor-in-Verilog-HDL RISC-CPU-Design-of-a-Single-Cycle-MIPS-Softcore-Processor-in-Verilog-HDL Public

    Softcore MIPS Processor : Single-Cycle RISC Architecture in Verilog HDL

    Verilog

  2. MAC32010-Chip-Digital-Low-Pass-Filter-Core_Custom-ASIC-Design MAC32010-Chip-Digital-Low-Pass-Filter-Core_Custom-ASIC-Design Public

    Custom ASIC implementation of a Verilog FIR low-pass filter core using OpenLane. Adapted RTL from an FPGA project and performed synthesis, floorplanning, placement, routing, and verification on Sky…

    Verilog

  3. RTL-Design-of-FIR-Filter-on-FPGA-using-Verilog RTL-Design-of-FIR-Filter-on-FPGA-using-Verilog Public

    Designed a FIR Filter with coefficients calculated in Python and implemented fixed-point arithmetic for FPGA processing.

    VHDL

  4. DDS-with-Uart-interface-on-FPGA DDS-with-Uart-interface-on-FPGA Public

    Direct Digital Synthesis on FPGA with UART for Oscillator-control

    VHDL

  5. SALVS-01-Specify-Animals-Location-Via-Sound SALVS-01-Specify-Animals-Location-Via-Sound Public

    SALVS-01: Specify Animals Location Via Sound, Novel Mission Ideas for Multiple Nano-satellites

  6. PIC18F4321_ADC_Monitoring_By_Register_Configuration PIC18F4321_ADC_Monitoring_By_Register_Configuration Public

    SWIG