Contest-specific DCP to FPGA Interchange Format Utility

[eddieh-xlnx]

This utility is used to convert a fully-routed Vivado Design Checkpoint (DCP) into the FPGA Interchange Format's Logical and Physical Netlists compatible with the FPGA24 contest.

Specifically, in line with the competition format the Physical Netlist will only contain the inter-site routing (i.e. PIPs) for global and static nets. All other nets will have their inter-site routing removed. Intra-site routing (not within the scope of this contest) is left as-is.

Example usage:

./gradlew -Dmain=com.xilinx.fpga24_routing_contest.DcpToFPGAIF :run --args="boom_soc_routed.dcp boom_soc.netlist boom_soc_unrouted.phys"

Compared to the benchmarks released in v1.0, the benchmarks in the upcoming v1.1 release contain nets with alternate sources set up, where available. Alternate sources typically refer to the ability for a LUT to exit its SLICE using up to 2 pins -- for an A6LUT these pins are A_O (always available) and AMUX (available if not used for another purpose). Considering both pins, where available, can improve routability, though there are no restrictions on which of the two (or whether both) source pins are used to connect to which sink pins.

Use of this utility is not necessary to enter the contest, though contestants may choose to use Vivado to compile additional benchmarks beyond those that we supply in order to increase test coverage/acquire more training data, etc.