I'm a PhD student at University of California, San Diego, with about 4 years of experience building ML accelerators. Besides digital circuit design, I enjoy teaching, community work, and backpacking.

• An open workflow for hardware research in FPGA/ASIC implementation of DNNs
• Developed software (python library) + hardware (SV modules, TCL flows) + firmware (C runtime)
• Started as self-motivated passion project; being integrated with HLS4ML library
• Software:
  • Python front-end to build & train models with Qkeras, run fixed point inference & generate SV, TCL, and C headers.
  • Made into pip package with Sphinx auto-documentation
  • Currently migrating backend from Qkeras to Brevitas
• Hardware:
  • Fully parameterized, dynamically reconfigurable, high performance AXI engine in SystemVerilog to fill a given area.
  • Built as a vehicle for hardware research, where users can switch custom MACs, and try their novel ideas.
  • Achieves 250 MHz on FPGA (ZCU104) and 1 GHz on TSMC 65nm LP. Being taped out with ARM SoCLabs
  • TCL scripts to generate SoC with AXI DMAs on Xilinx FPGAs, and for ASIC flow with a given PDK.
• Firmware
  • C firmware to control the DMAs & accelerator to process any given DNN.

• 64-hour hands-on short course, collaborating with Synopsys, teaching 271 participants from 13 countries
• Overwhelmingly positive feedback from undergraduate & industry professionals
• (Content)[https://github.com/skillsurf/systemverilog]:
  • Hands-on examples: Basics (full adder, counter) to complex (AXI-Stream Parameterized Matrix Multiplier with UART I/O)
  • Testing with randomized transactional testbenches
  • FPGA implementation & testing with Python
  • ASIC flow with Synopsys DesignCompiler & IC Compiler.

• Missing Semester:
  • An initiative I have started at my department, to conduct hands-on webminars to familarize students with tools and languages.
  • Free and open to anyone willing to learn
  • SystemVerilog webminar (above) was part of it.
• SoC Design for Vision Based Traffic Control
  • Undergraduate thesis project
  • Patent under review - private repo
  • Tensorflow 1.x, Keras, Python, C++, SystemVerilog, ZYNQ
• Vision Based Traffic Analytics
  • Commercializing - private repo
  • Group work
  • Python, Tensorflow 2.x, AWS, Node.js
• AbruTech Processor
  • My first big project in digital design
  • A custom processor on FPGA with our own architecture, ISA, assembler and simulator
  • Algorithms implemented: Downsampling, Upsampling RGB images, applying filters, prime finding with eratosthenes sieve
• Digital Graphic Equalizer
  • 3 bands, built for 5 extra marks